[rtems commit] bsps/riscv: Fix PLIC enable register count
Sebastian Huber
sebh at rtems.org
Thu Nov 10 14:04:57 UTC 2022
Module: rtems
Branch: master
Commit: bfdfc979fd272111b783986dbe1fc2f8ba14a466
Changeset: http://git.rtems.org/rtems/commit/?id=bfdfc979fd272111b783986dbe1fc2f8ba14a466
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Thu Nov 10 15:15:46 2022 +0100
bsps/riscv: Fix PLIC enable register count
Each PLIC enable register has 32 bits, so we have to divide by 32.
---
bsps/riscv/riscv/irq/irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 6fcaee172e..74d833eac8 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -245,10 +245,10 @@ static void riscv_plic_init(const void *fdt)
uint32_t cpu_index;
/*
- * Interrupt enable registers with 32-bit alignment based on
+ * Interrupt enable registers with 32-bit alignment based on
* number of interrupts.
*/
- enable_register_count = RTEMS_ALIGN_UP(ndev, 32);
+ enable_register_count = RTEMS_ALIGN_UP(ndev, 32) / 32;
hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
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