[rtems commit] bsps/riscv: Fix PLIC enable register count
Sebastian Huber
sebh at rtems.org
Wed Nov 23 06:43:33 UTC 2022
Module: rtems
Branch: master
Commit: d448aa4d05dee6007eb0c279c60c608ea7888c80
Changeset: http://git.rtems.org/rtems/commit/?id=d448aa4d05dee6007eb0c279c60c608ea7888c80
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Wed Nov 23 07:49:53 2022 +0100
bsps/riscv: Fix PLIC enable register count
---
bsps/riscv/riscv/irq/irq.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index 9266c2b2c7..4c19a07ae5 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -268,10 +268,12 @@ static void riscv_plic_init(const void *fdt)
uint32_t cpu_index;
/*
- * Interrupt enable registers with 32-bit alignment based on
- * number of interrupts.
+ * Each interrupt enable register contains exactly 32 enable bits.
+ * Calculate the enable register count based on the number of interrupts
+ * supported by the PLIC. Take the reserved interrupt ID zero into
+ * account.
*/
- enable_register_count = RTEMS_ALIGN_UP(ndev, 32) / 32;
+ enable_register_count = RTEMS_ALIGN_UP(ndev + 1, 32) / 32;
hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
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