RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1160
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160

* 9bdb83ab...b09bc600 - 2 commits from branch `main`

* cf932ed1 - riscv: Add support for Espressif Direct Boot
* cc17b5b7 - riscv: Add optional section copy callback
* a7d3731e - spec/bsps/riscv: Allow start section load address
* 02f52a77 - spec/riscv: Allow BSS to be specified independent of DATA
* ca7ba379 - riscv: Add support for vectored interrupt controllers
* 362608f2 - cpukit/riscv: Make use of MDT conditional on Zicsr
* 1ea3e0bc - riscv: Add basic ESP32-C3 BSP

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160
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