RTEMS | riscv: s-mode use SBI for timer, reset, and SMP support (!1108)

[Gedare Bloom (@gedare)]

Gedare Bloom commented on a discussion on bsps/riscv/riscv/clock/clockdrv.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108#note_145053

 >  }
 >  #endif /* !RISCV_USE_S_MODE */
 >  
 > -static void riscv_clock_at_tick(riscv_timecounter *tc)
 > +#ifdef RISCV_USE_S_MODE
 > +static bool riscv_has_isa_extension(const void *fdt, const char *ext)

This wound up pulling on a couple of threads, but I think it's going to make the RISC-V BSP family cleaner. I refactored this and a couple other functions into `bsps/riscv/shared/riscv-fdt.c` with an associated `bsp/riscv-fdt.h` header file.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108#note_145053
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