[PATCH] PR 2048: Removed use of PPC440 macro.
Ric Claus
claus at slac.stanford.edu
Fri Nov 30 23:21:20 UTC 2012
Retrying this patch as a stand alone patch and with fewer whitespace
differences. Also included are additional Book-E and PPC440 SPR definitions.
---
cpukit/score/cpu/powerpc/rtems/asm.h | 80 +----------
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 154 ++++++++++++++++---
2 files changed, 131 insertions(+), 103 deletions(-)
diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h
index b1a8870..594e323 100644
--- a/cpukit/score/cpu/powerpc/rtems/asm.h
+++ b/cpukit/score/cpu/powerpc/rtems/asm.h
@@ -176,11 +176,11 @@
#define usprg0 256
#define dar 0x013 /* Data Address Register */
-#define dec 0x016 /* Decrementer Register */
+#define dec 0x016 /* Decrementer Register */
#if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */
-#define dear 0x3d5
+#define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */
@@ -203,82 +203,6 @@
#define br6 0x086 /* DCR: memory bank register 6 */
#define br7 0x087 /* DCR: memory bank register 7 */
-#elif defined(ppc440)
-#define xer 0x001 /* SPR: Integer Exception Register */
-#define lr 0x008 /* SPR: Link Register */
-#define ctr 0x009 /* SPR: Count Register */
-#define pid 0x030 /* SPR: Process ID */
-#define decar 0x036 /* SPR: Decrementer Auto-Reload */
-#define dear 0x03d /* SPR: Data Exception Address Register */
-#define esr 0x03e /* SPR: Exception Syndrome Register */
-#define ivpr 0x03f /* SPR: Interrupt Vector Prefix Register */
-#define sprg4_w 0x104 /* SPR: Special Purpose Register General 4 (WO) */
-#define sprg5_w 0x105 /* SPR: Special Purpose Register General 5 (WO) */
-#define sprg6_w 0x107 /* SPR: Special Purpose Register General 6 (WO) */
-#define sprg7_w 0x108 /* SPR: Special Purpose Register General 7 (WO) */
-#define tbl 0x10c /* SPR: Time Base Lower */
-#define tbu 0x10d /* SPR: Time Base Upper */
-#define pir 0x11e /* SPR: Processor ID Register */
-#define pvr 0x11f /* SPR: Processor Version Register */
-#define dbsr 0x130 /* SPR: Debug Status Register */
-#define dbcr0 0x134 /* SPR: Debug Control Register 0 */
-#define dbcr1 0x135 /* SPR: Debug Control Register 1 */
-#define dbcr2 0x136 /* SPR: Debug Control Register 2 */
-#define iac1 0x138 /* SPR: Instruction Address Compare 1 */
-#define iac2 0x139 /* SPR: Instruction Address Compare 2 */
-#define iac3 0x13a /* SPR: Instruction Address Compare 3 */
-#define iac4 0x13b /* SPR: Instruction Address Compare 4 */
-#define dac1 0x13c /* SPR: Data Address Compare 1 */
-#define dac2 0x13d /* SPR: Data Address Compare 2 */
-#define dvc1 0x13e /* SPR: Data Value Compare 1 */
-#define dvc2 0x13f /* SPR: Data Value Compare 2 */
-#define tsr 0x150 /* SPR: Timer Status Register */
-#define tcr 0x154 /* SPR: Timer Control Register */
-#define ivor0 0x190 /* SPR: Interrupt Vector Offset Register 0 */
-#define ivor1 0x191 /* SPR: Interrupt Vector Offset Register 1 */
-#define ivor2 0x192 /* SPR: Interrupt Vector Offset Register 2 */
-#define ivor3 0x193 /* SPR: Interrupt Vector Offset Register 3 */
-#define ivor4 0x194 /* SPR: Interrupt Vector Offset Register 4 */
-#define ivor5 0x195 /* SPR: Interrupt Vector Offset Register 5 */
-#define ivor6 0x196 /* SPR: Interrupt Vector Offset Register 6 */
-#define ivor7 0x197 /* SPR: Interrupt Vector Offset Register 7 */
-#define ivor8 0x198 /* SPR: Interrupt Vector Offset Register 8 */
-#define ivor9 0x199 /* SPR: Interrupt Vector Offset Register 9 */
-#define ivor10 0x19a /* SPR: Interrupt Vector Offset Register 10 */
-#define ivor11 0x19b /* SPR: Interrupt Vector Offset Register 11 */
-#define ivor12 0x19c /* SPR: Interrupt Vector Offset Register 12 */
-#define ivor13 0x19d /* SPR: Interrupt Vector Offset Register 13 */
-#define ivor14 0x19e /* SPR: Interrupt Vector Offset Register 14 */
-#define ivor15 0x19f /* SPR: Interrupt Vector Offset Register 15 */
-#define mcsr 0x23c /* SPR: Machine Check Status Register */
-#define inv0 0x370 /* SPR: Instruction Cache Normal Victim 0 */
-#define inv1 0x371 /* SPR: Instruction Cache Normal Victim 1 */
-#define inv2 0x372 /* SPR: Instruction Cache Normal Victim 2 */
-#define inv3 0x373 /* SPR: Instruction Cache Normal Victim 3 */
-#define itv0 0x374 /* SPR: Instruction Cache Transient Victim 0 */
-#define itv1 0x375 /* SPR: Instruction Cache Transient Victim 1 */
-#define itv2 0x376 /* SPR: Instruction Cache Transient Victim 2 */
-#define itv3 0x377 /* SPR: Instruction Cache Transient Victim 3 */
-#define ccr1 0x378 /* SPR: Core Configuration Register 1 */
-#define dnv0 0x390 /* SPR: Data Cache Normal Victim 0 */
-#define dnv1 0x391 /* SPR: Data Cache Normal Victim 1 */
-#define dnv2 0x392 /* SPR: Data Cache Normal Victim 2 */
-#define dnv3 0x393 /* SPR: Data Cache Normal Victim 3 */
-#define dtv0 0x394 /* SPR: Data Cache Transient Victim 0 */
-#define dtv1 0x395 /* SPR: Data Cache Transient Victim 1 */
-#define dtv2 0x396 /* SPR: Data Cache Transient Victim 2 */
-#define dtv3 0x397 /* SPR: Data Cache Transient Victim 3 */
-#define dvlim 0x398 /* SPR: Data Cache Victim Limit */
-#define ivlim 0x399 /* SPR: Instruction Cache Victim Limit */
-#define rstcfg 0x39b /* SPR: Reset Configuration */
-#define dcdbtrl 0x39c /* SPR: Data Cache Debug Tag Register Low */
-#define dcdbtrh 0x39d /* SPR: Data Cache Debug Tag Register High */
-#define icdbtrl 0x39e /* SPR: Instruction Cache Debug Tag Register Low */
-#define icdbtrh 0x39f /* SPR: Instruction Cache Debug Tag Register High */
-#define mmucr 0x3b2 /* SPR: Memory Management Unit Control Register */
-#define ccr0 0x3b3 /* SPR: Core Configuration Register 0 */
-#define icdbdr 0x3d3 /* SPR: Instruction Cache Debug Data Register */
-#define dbdr 0x3f3 /* SPR: Debug Data Register */
/* end of IBM400 series register definitions */
#elif defined(mpc555)
diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index 2eb9235..008e387 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -20,8 +20,10 @@
#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */
#define MSR_SPE (1<<25) /* SPE enable (e500) */
+#define MSR_AP (1<<25) /* Auxiliary processor available */
+#define MSR_APE (1<<19) /* APU exception enable */
#define MSR_POW (1<<18) /* Enable Power Management */
-#define MSR_WE (1<<18) /* Wait state enable (e500) */
+#define MSR_WE (1<<18) /* Wait state enable (e500, 4xx) */
#define MSR_TGPR (1<<17) /* TLB Update registers in use */
#define MSR_CE (1<<17) /* BookE critical interrupt */
#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
@@ -32,6 +34,7 @@
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */
#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */
+#define MSR_DWE (1<<10) /* Debug wait enable (4xx) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* BookE debug exception */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
@@ -209,12 +212,12 @@ n:
* is different from that of 7400 and 7410.
* Though not used in 7400 and 7410, it is appeded with _745x just
* to be clarified.
- */
+ */
#define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */
#define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */
#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x)
#define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */
-
+
#define L3CR 1018 /* PPC 7450/7455 L3 control register */
#define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */
#define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */
@@ -319,18 +322,119 @@ lidate */
#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13)
#define BOOKE_TCR_FPEXT_MASK (0xf<<13)
-#define BOOKE_PID 48
-#define BOOKE_ESR 62
-#define BOOKE_IVPR 63
-#define BOOKE_PIR 286
-#define BOOKE_DBSR 304
-#define BOOKE_DBCR0 308
-#define BOOKE_DBCR1 309
-#define BOOKE_DBCR2 310
-#define BOOKE_DAC1 316
-#define BOOKE_DAC2 317
-#define BOOKE_DVC1 318
-#define BOOKE_DVC2 319
+#define BOOKE_PID 48 /* Process ID */
+#define BOOKE_CSRR0 58 /* Critical Save/Restore Register 0 */
+#define BOOKE_CSRR1 59 /* Critical Save/Restore Register 1 */
+#define BOOKE_ESR 62 /* Exception Syndrome Register */
+#define BOOKE_IVPR 63 /* Interrupt Vector Prefix Register */
+#define BOOKE_SPRG4_W 260 /* Special Purpose Register General 4 (WO) */
+#define BOOKE_SPRG5_W 261 /* Special Purpose Register General 5 (WO) */
+#define BOOKE_SPRG6_W 262 /* Special Purpose Register General 6 (WO) */
+#define BOOKE_SPRG7_W 263 /* Special Purpose Register General 7 (WO) */
+#define BOOKE_PIR 286 /* Processor ID Register */
+#define BOOKE_DBSR 304 /* Debug Status Register */
+#define BOOKE_DBCR0 308 /* Debug Control Register 0 */
+#define BOOKE_DBCR1 309 /* Debug Control Register 1 */
+#define BOOKE_DBCR2 310 /* Debug Control Register 2 */
+#define BOOKE_IAC1 312 /* Instruction Address Compare 1 */
+#define BOOKE_IAC2 313 /* Instruction Address Compare 2 */
+#define BOOKE_IAC3 314 /* Instruction Address Compare 3 */
+#define BOOKE_IAC4 315 /* Instruction Address Compare 4 */
+#define BOOKE_DAC1 316 /* Data Address Compare 1 */
+#define BOOKE_DAC2 317 /* Data Address Compare 2 */
+#define BOOKE_DVC1 318 /* Data Value Compare 1 */
+#define BOOKE_DVC2 319 /* Data Value Compare 2 */
+#define BOOKE_IVOR0 400 /* Interrupt Vector Offset Register 0 */
+#define BOOKE_IVOR1 401 /* Interrupt Vector Offset Register 1 */
+#define BOOKE_IVOR2 402 /* Interrupt Vector Offset Register 2 */
+#define BOOKE_IVOR3 403 /* Interrupt Vector Offset Register 3 */
+#define BOOKE_IVOR4 404 /* Interrupt Vector Offset Register 4 */
+#define BOOKE_IVOR5 405 /* Interrupt Vector Offset Register 5 */
+#define BOOKE_IVOR6 406 /* Interrupt Vector Offset Register 6 */
+#define BOOKE_IVOR7 407 /* Interrupt Vector Offset Register 7 */
+#define BOOKE_IVOR8 408 /* Interrupt Vector Offset Register 8 */
+#define BOOKE_IVOR9 409 /* Interrupt Vector Offset Register 9 */
+#define BOOKE_IVOR10 410 /* Interrupt Vector Offset Register 10 */
+#define BOOKE_IVOR11 411 /* Interrupt Vector Offset Register 11 */
+#define BOOKE_IVOR12 412 /* Interrupt Vector Offset Register 12 */
+#define BOOKE_IVOR13 413 /* Interrupt Vector Offset Register 13 */
+#define BOOKE_IVOR14 414 /* Interrupt Vector Offset Register 14 */
+#define BOOKE_IVOR15 415 /* Interrupt Vector Offset Register 15 */
+#define BOOKE_MCSRR0 570 /* Machine Check Save/Restore Register 0 */
+#define BOOKE_MCSRR1 571 /* Machine Check Save/Restore Register 1 */
+#define BOOKE_MCSR 572 /* Machine Check Status Register */
+
+#define PPC440_INV0 880 /* Instruction Cache Normal Victim 0 */
+#define PPC440_INV1 881 /* Instruction Cache Normal Victim 1 */
+#define PPC440_INV2 882 /* Instruction Cache Normal Victim 2 */
+#define PPC440_INV3 883 /* Instruction Cache Normal Victim 3 */
+#define PPC440_ITV0 884 /* Instruction Cache Transient Victim 0 */
+#define PPC440_ITV1 885 /* Instruction Cache Transient Victim 1 */
+#define PPC440_ITV2 886 /* Instruction Cache Transient Victim 2 */
+#define PPC440_ITV3 887 /* Instruction Cache Transient Victim 3 */
+#define PPC440_CCR1 888 /* Core Configuration Register 1 */
+#define PPC440_DNV0 912 /* Data Cache Normal Victim 0 */
+#define PPC440_DNV1 913 /* Data Cache Normal Victim 1 */
+#define PPC440_DNV2 914 /* Data Cache Normal Victim 2 */
+#define PPC440_DNV3 915 /* Data Cache Normal Victim 3 */
+#define PPC440_DTV0 916 /* Data Cache Transient Victim 0 */
+#define PPC440_DTV1 917 /* Data Cache Transient Victim 1 */
+#define PPC440_DTV2 918 /* Data Cache Transient Victim 2 */
+#define PPC440_DTV3 919 /* Data Cache Transient Victim 3 */
+#define PPC440_DVLIM 920 /* Data Cache Victim Limit */
+#define PPC440_IVLIM 921 /* Instruction Cache Victim Limit */
+#define PPC440_RSTCFG 923 /* Reset Configuration */
+#define PPC440_DCDBTRL 924 /* Data Cache Debug Tag Register Low */
+#define PPC440_DCDBTRH 925 /* Data Cache Debug Tag Register High */
+#define PPC440_ICDBTRL 926 /* Instruction Cache Debug Tag Register Low */
+#define PPC440_ICDBTRH 927 /* Instruction Cache Debug Tag Register High */
+#define PPC440_MMUCR 946 /* Memory Management Unit Control Register */
+#define PPC440_CCR0 947 /* Core Configuration Register 0 */
+#define PPC440_ICDBDR 979 /* Instruction Cache Debug Data Register */
+#define PPC440_DBDR 1011 /* Debug Data Register */
+
+#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Etended Page Number */
+#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
+#define PPC440_TLB0_V ( 1 << (31-22)) /* Entry valid */
+#define PPC440_TLB0_TS ( 1 << (31-23)) /* Translation space */
+#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27)) /* Page size */
+#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf)
+#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31)) /* Tag Parity */
+#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf)
+
+#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31)) /* Translation ID */
+#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff)
+
+#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Real Page Number */
+#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1))
+#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23)) /* Parity for TLB word 1 */
+#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3)
+#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31)) /* Extended Real Page No. */
+#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf)
+
+#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1)) /* Parity for TLB word 2 */
+#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3)
+#define PPC440_TLB2_U0 ( 1 << (31-16)) /* User attr. 0 */
+#define PPC440_TLB2_U1 ( 1 << (31-17)) /* User attr. 1 */
+#define PPC440_TLB2_U2 ( 1 << (31-18)) /* User attr. 2 */
+#define PPC440_TLB2_U3 ( 1 << (31-19)) /* User attr. 3 */
+#define PPC440_TLB2_W ( 1 << (31-20)) /* Write-through */
+#define PPC440_TLB2_I ( 1 << (31-21)) /* Cache-inhibited */
+#define PPC440_TLB2_M ( 1 << (31-22)) /* Memory-coherence req. */
+#define PPC440_TLB2_G ( 1 << (31-23)) /* Guarded */
+#define PPC440_TLB2_E ( 1 << (31-24)) /* Little-endian */
+#define PPC440_TLB2_UX ( 1 << (31-26)) /* User exec. */
+#define PPC440_TLB2_UW ( 1 << (31-27)) /* User write */
+#define PPC440_TLB2_UR ( 1 << (31-28)) /* User read */
+#define PPC440_TLB2_SX ( 1 << (31-29)) /* Super exec. */
+#define PPC440_TLB2_SW ( 1 << (31-30)) /* Super write */
+#define PPC440_TLB2_SR ( 1 << (31-31)) /* Super read */
+
+#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 )
+#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff )
+
+#define PPC440_TLB2_PERM(n) ( (n) & 0x3f )
+#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f )
/* Freescale Book E Implementation Standards (EIS): Branch Operations */
@@ -442,9 +546,9 @@ lidate */
/* Freescale Book E Implementation Standards (EIS): Interrupt */
-#define FSL_EIS_MCAR 573
-#define FSL_EIS_DSRR0 574
-#define FSL_EIS_DSRR1 575
+#define FSL_EIS_MCAR 573
+#define FSL_EIS_DSRR0 574
+#define FSL_EIS_DSRR1 575
/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */
@@ -452,16 +556,16 @@ lidate */
/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */
-#define FSL_EIS_SPRG8 604
-#define FSL_EIS_SPRG9 605
+#define FSL_EIS_SPRG8 604
+#define FSL_EIS_SPRG9 605
/* Freescale Book E Implementation Standards (EIS): Debug */
-#define FSL_EIS_DBCR3 561
-#define FSL_EIS_DBCR4 563
-#define FSL_EIS_DBCR5 564
-#define FSL_EIS_DBCR6 603
-#define FSL_EIS_DBCNT 562
+#define FSL_EIS_DBCR3 561
+#define FSL_EIS_DBCR4 563
+#define FSL_EIS_DBCR5 564
+#define FSL_EIS_DBCR6 603
+#define FSL_EIS_DBCNT 562
/**
* @brief Default value for the interrupt disable mask.
--
1.7.1
More information about the devel
mailing list