[PATCH] ARM: Prevent _ARMV4_Exception_fiq_default from re-enabling FIQs.

[Martin Galvan]

Follow-up from here:

https://lists.rtems.org/pipermail/devel/2015-February/009974.html

When talking to Sebastian Huber about the behavior of _ARMV4_Exception_fiq_default, he mentioned that it shouldn't re-enable FIQs again. This patch sets the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't enable the FIQs.

So far I've tested it on the TMS570 and it seems to be working fine (we were getting endless FIQs before, now we end up in bsp_reset). However, I'm not sure if there are other BSPs out there that rely on the previous behavior.

diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
index a0ee46c..a10de30 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
 	stmdb	sp!, {r0-r12}
 	mov	r4, #7

+	/*
+	 * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
+	 * (which we'll load into the CPSR in save_more_context).
+	 */
+	mrs r2, spsr
+	orr r2, #ARM_PSR_F
+	msr spsr_c, r2
+
 save_more_context:

 	/* Save more context */