[PATCH 018/111] LEON: replaced old BSP PCI layer with new generic libpci PCI layer
Daniel Hellstrom
daniel at gaisler.com
Thu Feb 26 16:38:20 UTC 2015
The old code used a limited PCI configuration library, which was
duplicated into LEON2 and LEON3 BSP pci.c together with respective
Host controller PCI interface.
The LEON2 BSP had support for AT697 PCI, and LEON3 for GRPCI PCI
Host controller. With this update new PCI Host drivers are added,
and all support the new generic PCI Library:
* AT697 PCI (LEON2 only)
* GRPCI (LEON2-GRLIB and LEON3)
* GRPCI2 (LEON2-GRLIB and LEON3)
* Actel PCIF GRLIB Wrapper (LEON3 only)
The LEON2 BSP is defined as big-endian PCI in bsp.h, since the
AT697 supports only big-endian PCI.
---
c/src/lib/libbsp/sparc/Makefile.am | 8 +-
c/src/lib/libbsp/sparc/leon2/Makefile.am | 9 +-
c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c | 656 ++++++++++++++
c/src/lib/libbsp/sparc/leon2/pci/pci.c | 730 ----------------
c/src/lib/libbsp/sparc/leon2/preinstall.am | 4 -
c/src/lib/libbsp/sparc/leon3/Makefile.am | 9 +-
c/src/lib/libbsp/sparc/leon3/pci/pci.c | 613 -------------
c/src/lib/libbsp/sparc/leon3/preinstall.am | 6 +-
c/src/lib/libbsp/sparc/shared/include/grpci2.h | 61 ++
c/src/lib/libbsp/sparc/shared/include/pci.h | 56 --
c/src/lib/libbsp/sparc/shared/pci/grpci.c | 687 +++++++++++++++
c/src/lib/libbsp/sparc/shared/pci/grpci2.c | 902 ++++++++++++++++++++
.../libbsp/sparc/shared/pci/pci_memreg_sparc_be.c | 27 +
.../libbsp/sparc/shared/pci/pci_memreg_sparc_le.c | 28 +
c/src/lib/libbsp/sparc/shared/pci/pcif.c | 563 ++++++++++++
c/src/lib/libbsp/sparc/shared/pci/pcifinddevice.c | 51 --
16 files changed, 2947 insertions(+), 1463 deletions(-)
create mode 100644 c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
delete mode 100644 c/src/lib/libbsp/sparc/leon2/pci/pci.c
delete mode 100644 c/src/lib/libbsp/sparc/leon3/pci/pci.c
create mode 100644 c/src/lib/libbsp/sparc/shared/include/grpci2.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/pci.h
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/grpci.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/grpci2.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_be.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_le.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/pcif.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/pci/pcifinddevice.c
diff --git a/c/src/lib/libbsp/sparc/Makefile.am b/c/src/lib/libbsp/sparc/Makefile.am
index d733ca1..0d61a41 100644
--- a/c/src/lib/libbsp/sparc/Makefile.am
+++ b/c/src/lib/libbsp/sparc/Makefile.am
@@ -35,8 +35,12 @@ EXTRA_DIST += shared/timer/tlib.c
EXTRA_DIST += shared/timer/tlib_ckinit.c
# PCI bus
-EXTRA_DIST += shared/include/pci.h
-EXTRA_DIST += shared/pci/pcifinddevice.c
+EXTRA_DIST += shared/include/grpci2.h
+EXTRA_DIST += shared/pci/grpci.c
+EXTRA_DIST += shared/pci/grpci2.c
+EXTRA_DIST += shared/pci/pcif.c
+EXTRA_DIST += shared/pci/pci_memreg_sparc_le.c
+EXTRA_DIST += shared/pci/pci_memreg_sparc_be.c
# DEBUG
EXTRA_DIST += shared/include/debug_defs.h
diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am
index e9dcfd8..ba98665 100644
--- a/c/src/lib/libbsp/sparc/leon2/Makefile.am
+++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am
@@ -24,7 +24,6 @@ include_HEADERS += ../../sparc/shared/include/b1553brm.h
include_HEADERS += ../../sparc/shared/include/b1553brm_pci.h
include_HEADERS += ../../sparc/shared/include/b1553brm_rasta.h
include_HEADERS += ../../sparc/shared/include/debug_defs.h
-include_HEADERS += ../../sparc/shared/include/pci.h
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -109,7 +108,13 @@ libbsp_a_SOURCES += ../../sparc/shared/timer/gptimer.c
libbsp_a_SOURCES += ../../sparc/shared/timer/tlib.c
# PCI
-libbsp_a_SOURCES += pci/pci.c ../../sparc/shared/pci/pcifinddevice.c
+include_HEADERS += ../../sparc/shared/include/grpci2.h
+libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/grpci.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_le.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c
+libbsp_a_SOURCES += pci/at697_pci.c
+
# RASTA Kit
libbsp_a_SOURCES += rasta/rasta.c
# Companion Chip Kit
diff --git a/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c b/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
new file mode 100644
index 0000000..2387cc0
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c
@@ -0,0 +1,656 @@
+/* LEON2 AT697 PCI Host Driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the AT697 PCI core and initialize,
+ * - the PCI Library (pci.c)
+ * - the general part of the PCI Bus driver (pci_bus.c)
+ *
+ * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
+ * default taken from Plug and Play, but may be overridden by the
+ * driver resources INTA#..INTD#.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+/* Configurable parameters
+ * =======================
+ * INT[A..D]# Select system IRQ (can be tranlated into I/O interrupt)
+ * INT[A..D]#_PIO Select PIO used to generate I/O interrupt
+ *
+ * Notes
+ * =====
+ * IRQ must not be enabled before all PCI boards have been enabled, the
+ * IRQ is therefore enabled first in init2. The init2() for this driver
+ * is assumed to be executed earlier that all boards and their devices
+ * driver's init2() function.
+ *
+ */
+
+#include <rtems/bspIo.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <libcpu/byteorder.h>
+#include <libcpu/access.h>
+#include <pci.h>
+#include <pci/cfg.h>
+
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/pci_bus.h>
+#include <drvmgr/leon2_amba_bus.h>
+
+#include <leon.h>
+
+/* Configuration options */
+
+#define SYSTEM_MAINMEM_START 0x40000000
+#define SYSTEM_MAINMEM_START2 0x60000000
+
+/* Interrupt assignment. Set to other value than 0xff in order to
+ * override defaults and plug&play information
+ */
+#ifndef AT697_INTA_SYSIRQ
+ #define AT697_INTA_SYSIRQ 0xff
+#endif
+#ifndef AT697_INTB_SYSIRQ
+ #define AT697_INTB_SYSIRQ 0xff
+#endif
+#ifndef AT697_INTC_SYSIRQ
+ #define AT697_INTC_SYSIRQ 0xff
+#endif
+#ifndef AT697_INTD_SYSIRQ
+ #define AT697_INTD_SYSIRQ 0xff
+#endif
+
+#ifndef AT697_INTA_PIO
+ #define AT697_INTA_PIO 0xff
+#endif
+#ifndef AT697_INTB_PIO
+ #define AT697_INTB_PIO 0xff
+#endif
+#ifndef AT697_INTC_PIO
+ #define AT697_INTC_PIO 0xff
+#endif
+#ifndef AT697_INTD_PIO
+ #define AT697_INTD_PIO 0xff
+#endif
+
+
+/* AT697 PCI */
+#define AT697_PCI_REG_ADR 0x80000100
+
+/* PCI Window used */
+#define PCI_MEM_START 0xa0000000
+#define PCI_MEM_END 0xf0000000
+#define PCI_MEM_SIZE (PCI_MEM_END - PCI_MEM_START)
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif
+
+#define PCI_INVALID_VENDORDEVICEID 0xffffffff
+#define PCI_MULTI_FUNCTION 0x80
+
+struct at697pci_regs {
+ volatile unsigned int pciid1; /* 0x80000100 - PCI Device identification register 1 */
+ volatile unsigned int pcisc; /* 0x80000104 - PCI Status & Command */
+ volatile unsigned int pciid2; /* 0x80000108 - PCI Device identification register 2 */
+ volatile unsigned int pcibhlc; /* 0x8000010c - BIST, Header type, Cache line size register */
+ volatile unsigned int mbar1; /* 0x80000110 - Memory Base Address Register 1 */
+ volatile unsigned int mbar2; /* 0x80000114 - Memory Base Address Register 2 */
+ volatile unsigned int iobar3; /* 0x80000118 - IO Base Address Register 3 */
+ volatile unsigned int dummy1[4]; /* 0x8000011c - 0x80000128 */
+ volatile unsigned int pcisid; /* 0x8000012c - Subsystem identification register */
+ volatile unsigned int dummy2; /* 0x80000130 */
+ volatile unsigned int pcicp; /* 0x80000134 - PCI capabilities pointer register */
+ volatile unsigned int dummy3; /* 0x80000138 */
+ volatile unsigned int pcili; /* 0x8000013c - PCI latency interrupt register */
+ volatile unsigned int pcirt; /* 0x80000140 - PCI retry, trdy config */
+ volatile unsigned int pcicw; /* 0x80000144 - PCI configuration write register */
+ volatile unsigned int pcisa; /* 0x80000148 - PCI Initiator Start Address */
+ volatile unsigned int pciiw; /* 0x8000014c - PCI Initiator Write Register */
+ volatile unsigned int pcidma; /* 0x80000150 - PCI DMA configuration register */
+ volatile unsigned int pciis; /* 0x80000154 - PCI Initiator Status Register */
+ volatile unsigned int pciic; /* 0x80000158 - PCI Initiator Configuration */
+ volatile unsigned int pcitpa; /* 0x8000015c - PCI Target Page Address Register */
+ volatile unsigned int pcitsc; /* 0x80000160 - PCI Target Status-Command Register */
+ volatile unsigned int pciite; /* 0x80000164 - PCI Interrupt Enable Register */
+ volatile unsigned int pciitp; /* 0x80000168 - PCI Interrupt Pending Register */
+ volatile unsigned int pciitf; /* 0x8000016c - PCI Interrupt Force Register */
+ volatile unsigned int pcid; /* 0x80000170 - PCI Data Register */
+ volatile unsigned int pcibe; /* 0x80000174 - PCI Burst End Register */
+ volatile unsigned int pcidmaa; /* 0x80000178 - PCI DMA Address Register */
+};
+
+/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
+ * to a system interrupt number.
+ */
+unsigned char at697_pci_irq_table[4] =
+{
+ /* INTA# */ AT697_INTA_SYSIRQ,
+ /* INTB# */ AT697_INTB_SYSIRQ,
+ /* INTC# */ AT697_INTC_SYSIRQ,
+ /* INTD# */ AT697_INTD_SYSIRQ
+};
+
+/* PCI Interrupt PIO assignment. Selects which GPIO pin will be used to
+ * generate the system IRQ.
+ *
+ * PCI IRQ -> GPIO -> 4 x I/O select -> System IRQ
+ * ^- pio_table ^- irq_select
+ */
+unsigned char at697_pci_irq_pio_table[4] =
+{
+ /* INTA# */ AT697_INTA_PIO,
+ /* INTB# */ AT697_INTB_PIO,
+ /* INTC# */ AT697_INTC_PIO,
+ /* INTD# */ AT697_INTD_PIO
+};
+
+/* Driver private data struture */
+struct at697pci_priv {
+ struct drvmgr_dev *dev;
+ struct at697pci_regs *regs;
+ int minor;
+
+ uint32_t devVend; /* PCI Device and Vendor ID of Host */
+ uint32_t bar1_pci_adr;
+ uint32_t bar2_pci_adr;
+
+ struct drvmgr_map_entry maps_up[3];
+ struct drvmgr_map_entry maps_down[2];
+ struct pcibus_config config;
+};
+
+struct at697pci_priv *at697pcipriv = NULL;
+static int at697pci_minor = 0;
+
+int at697pci_init1(struct drvmgr_dev *dev);
+int at697pci_init2(struct drvmgr_dev *dev);
+
+/* AT697 PCI DRIVER */
+
+struct drvmgr_drv_ops at697pci_ops =
+{
+ .init = {at697pci_init1, at697pci_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct leon2_amba_dev_id at697pci_ids[] =
+{
+ {LEON2_AMBA_AT697PCI_ID},
+ {0} /* Mark end of table */
+};
+
+struct leon2_amba_drv_info at697pci_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_LEON2_AMBA_AT697PCI, /* Driver ID */
+ "AT697PCI_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_LEON2_AMBA, /* Bus Type */
+ &at697pci_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct at697pci_priv), /* let drvmgr alloc private */
+ },
+ &at697pci_ids[0]
+};
+
+void at697pci_register_drv(void)
+{
+ DBG("Registering AT697 PCI driver\n");
+ drvmgr_drv_register(&at697pci_info.general);
+}
+
+/* The configuration access functions uses the DMA functionality of the
+ * AT697 pci controller to be able access all slots
+ */
+
+int at697pci_cfg_r32(pci_dev_t dev, int offset, uint32_t *val)
+{
+ struct at697pci_regs *regs;
+ volatile unsigned int data = 0;
+ unsigned int address;
+ int bus = PCI_DEV_BUS(dev);
+ int slot = PCI_DEV_SLOT(dev);
+ int func = PCI_DEV_FUNC(dev);
+ int retval;
+
+ if (slot > 21 || (offset & ~0xfc)) {
+ *val = 0xffffffff;
+ return PCISTS_EINVAL;
+ }
+
+ regs = at697pcipriv->regs;
+
+ regs->pciitp = 0xff; /* clear interrupts */
+
+ if ( bus == 0 ) {
+ /* PCI Access - TYPE 0 */
+ address = (1<<(11+slot)) | (func << 8) | offset;
+ } else {
+ /* PCI access - TYPE 1 */
+ address = ((bus & 0xff) << 16) | ((slot & 0x1f) << 11) |
+ (func << 8) | offset | 1;
+ }
+ regs->pcisa = address;
+ regs->pcidma = 0xa01;
+ regs->pcidmaa = (unsigned int) &data;
+
+ while (regs->pciitp == 0)
+ ;
+
+ regs->pciitp = 0xff; /* clear interrupts */
+
+ if (regs->pcisc & 0x20000000) { /* Master Abort */
+ regs->pcisc |= 0x20000000;
+ *val = 0xffffffff;
+ retval = PCISTS_MSTABRT;
+ } else {
+ *val = data;
+ retval = PCISTS_OK;
+ }
+
+ DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
+ bus, slot, func, offset, address, *val);
+
+ return retval;
+}
+
+int at697pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
+ *val = 0xffff & (v >> (8*(ofs & 0x3)));
+
+ return retval;
+}
+
+int at697pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
+
+ *val = 0xff & (v >> (8*(ofs & 3)));
+
+ return retval;
+}
+
+int at697pci_cfg_w32(pci_dev_t dev, int offset, uint32_t val)
+{
+ struct at697pci_regs *regs;
+ volatile unsigned int tmp_val = val;
+ unsigned int address;
+ int bus = PCI_DEV_BUS(dev);
+ int slot = PCI_DEV_SLOT(dev);
+ int func = PCI_DEV_FUNC(dev);
+ int retval;
+
+ if (slot > 21 || (offset & ~0xfc))
+ return PCISTS_EINVAL;
+
+ regs = at697pcipriv->regs;
+
+ regs->pciitp = 0xff; /* clear interrupts */
+
+ if ( bus == 0 ) {
+ /* PCI Access - TYPE 0 */
+ address = (1<<(11+slot)) | (func << 8) | offset;
+ } else {
+ /* PCI access - TYPE 1 */
+ address = ((bus & 0xff) << 16) | ((slot & 0x1f) << 11) |
+ (func << 8) | offset | 1;
+ }
+ regs->pcisa = address;
+ regs->pcidma = 0xb01;
+ regs->pcidmaa = (unsigned int) &tmp_val;
+
+ while (regs->pciitp == 0)
+ ;
+
+ if (regs->pcisc & 0x20000000) { /* Master Abort */
+ regs->pcisc |= 0x20000000;
+ retval = PCISTS_MSTABRT;
+ } else
+ retval = PCISTS_OK;
+
+ regs->pciitp = 0xff; /* clear interrupts */
+
+ DBG("pci_write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
+ bus, slot, func, offset, address, val);
+
+ return retval;
+}
+
+int at697pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
+
+ return at697pci_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+int at697pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
+{
+ uint32_t v;
+
+ at697pci_cfg_r32(dev, ofs & ~0x3, &v);
+
+ v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
+
+ return at697pci_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+/* Return the assigned system IRQ number that corresponds to the PCI
+ * "Interrupt Pin" information from configuration space.
+ *
+ * The IRQ information is stored in the at697_pci_irq_table configurable
+ * by the user.
+ *
+ * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
+ * 0xff if not assigned.
+ */
+uint8_t at697pci_bus0_irq_map(pci_dev_t dev, int irq_pin)
+{
+ uint8_t sysIrqNr = 0; /* not assigned */
+ int irq_group;
+
+ if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
+ /* Use default IRQ decoding on PCI BUS0 according slot numbering */
+ irq_group = PCI_DEV_SLOT(dev) & 0x3;
+ irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
+ /* Valid PCI "Interrupt Pin" number */
+ sysIrqNr = at697_pci_irq_table[irq_pin];
+ }
+ return sysIrqNr;
+}
+
+int at697pci_translate(uint32_t *address, int type, int dir)
+{
+ /* No address translation implmented at this point */
+ return 0;
+}
+
+extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
+
+/* AT697 Big-Endian PCI access routines */
+struct pci_access_drv at697pci_access_drv = {
+ .cfg =
+ {
+ at697pci_cfg_r8,
+ at697pci_cfg_r16,
+ at697pci_cfg_r32,
+ at697pci_cfg_w8,
+ at697pci_cfg_w16,
+ at697pci_cfg_w32,
+ },
+ .io =
+ { /* AT697 only supports non-standard Big-Endian PCI Bus */
+ _ld8,
+ _ld_be16,
+ _ld_be32,
+ _st8,
+ _st_be16,
+ _st_be32,
+
+ },
+ .memreg = &pci_memreg_sparc_be_ops,
+ .translate = at697pci_translate,
+};
+
+/* Initializes the AT697PCI core hardware
+ *
+ */
+int at697pci_hw_init(struct at697pci_priv *priv)
+{
+ struct at697pci_regs *regs = priv->regs;
+ unsigned short vendor = regs->pciid1 >> 16;
+ pci_dev_t host = PCI_DEV(0, 0, 0);
+
+ /* Must match ATMEL or ESA ID */
+ if ( !((vendor == 0x1202) || (vendor == 0x1E0F)) ) {
+ /* No AT697 PCI, quit */
+ return -1;
+ }
+
+ /* Reset PCI Core */
+ regs->pciic = 0xffffffff;
+
+ /* Mask PCI interrupts */
+ regs->pciite = 0;
+
+ /* Map parts of AT697 main memory into PCI (for DMA) */
+ regs->mbar1 = priv->bar1_pci_adr;
+ regs->mbar2 = priv->bar2_pci_adr;
+ regs->pcitpa = (priv->bar1_pci_adr & 0xff000000) |
+ ((priv->bar2_pci_adr>>16) & 0xff00);
+
+ /* Enable PCI master and target memory command response */
+ regs->pcisc |= 0x40 | 0x6;
+
+ /* Set latency timer to 64 */
+ regs->pcibhlc = 0x00004000;
+
+ /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
+ regs->pciic = 0x41;
+
+ /* Get the AT697PCI Host PCI ID */
+ at697pci_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+
+ return 0;
+}
+
+/* Initializes the AT697PCI core and driver, must be called before calling init_pci()
+ *
+ * Return values
+ * 0 Successful initalization
+ * -1 Error during initialization.
+ */
+int at697pci_init(struct at697pci_priv *priv)
+{
+ int pin;
+ union drvmgr_key_value *value;
+ char keyname_sysirq[6];
+ char keyname_pio[10];
+
+ /* PCI core, init private structure */
+ priv->regs = (struct at697pci_regs *) AT697_PCI_REG_ADR;
+
+ /* Init PCI interrupt assignment table to all use the interrupt routed
+ * through the GPIO core.
+ *
+ * INT[A..D]# selects system IRQ (and I/O interrupt)
+ * INT[A..D]#_PIO selects PIO used to generate I/O interrupt
+ */
+ strcpy(keyname_sysirq, "INTX#");
+ strcpy(keyname_pio, "INTX#_PIO");
+ for (pin=1; pin<5; pin++) {
+ if ( at697_pci_irq_table[pin-1] == 0xff ) {
+ /* User may override hardcoded IRQ setup */
+ keyname_sysirq[3] = 'A' + (pin-1);
+ value = drvmgr_dev_key_get(priv->dev,
+ keyname_sysirq, KEY_TYPE_INT);
+ if ( value )
+ at697_pci_irq_table[pin-1] = value->i;
+ }
+ if ( at697_pci_irq_pio_table[pin-1] == 0xff ) {
+ /* User may override hardcoded IRQ setup */
+ keyname_pio[3] = 'A' + (pin-1);
+ value = drvmgr_dev_key_get(priv->dev,
+ keyname_pio, KEY_TYPE_INT);
+ if ( value )
+ at697_pci_irq_pio_table[pin-1] = value->i;
+ }
+ }
+
+ /* Use GRPCI target BAR1 and BAR2 to map CPU RAM to PCI, this is to
+ * make it possible for PCI peripherals to do DMA directly to CPU memory
+ *
+ * Defualt is to map system RAM at pci address 0x40000000 and system
+ * SDRAM to pci address 0x60000000
+ */
+ value = drvmgr_dev_key_get(priv->dev, "tgtbar1", KEY_TYPE_INT);
+ if (value)
+ priv->bar1_pci_adr = value->i;
+ else
+ priv->bar1_pci_adr = SYSTEM_MAINMEM_START; /* default */
+
+ value = drvmgr_dev_key_get(priv->dev, "tgtbar2", KEY_TYPE_INT);
+ if (value)
+ priv->bar2_pci_adr = value->i;
+ else
+ priv->bar2_pci_adr = SYSTEM_MAINMEM_START2; /* default */
+
+ /* Init the PCI Core */
+ if ( at697pci_hw_init(priv) ) {
+ return -3;
+ }
+
+ /* Down streams translation table */
+ priv->maps_down[0].name = "AMBA -> PCI MEM Window";
+ priv->maps_down[0].size = 0xF0000000 - 0xA0000000;
+ priv->maps_down[0].from_adr = (void *)0xA0000000;
+ priv->maps_down[0].to_adr = (void *)0xA0000000;
+ /* End table */
+ priv->maps_down[1].size = 0;
+
+ /* Up streams translation table, 2x16Mb mapped 1:1 */
+ priv->maps_up[0].name = "Target BAR0 -> AMBA";
+ priv->maps_up[0].size = 0x01000000; /* 16Mb BAR1 */
+ priv->maps_up[0].from_adr = (void *)priv->bar1_pci_adr;
+ priv->maps_up[0].to_adr = (void *)priv->bar1_pci_adr;
+ priv->maps_up[1].name = "Target BAR1 -> AMBA";
+ priv->maps_up[1].size = 0x01000000; /* 16Mb BAR2 */
+ priv->maps_up[1].from_adr = (void *)priv->bar2_pci_adr;
+ priv->maps_up[1].to_adr = (void *)priv->bar2_pci_adr;
+ /* End table */
+ priv->maps_up[2].size = 0;
+
+ return 0;
+}
+
+/* Called when a core is found with the AMBA device and vendor ID
+ * given in at697pci_ids[].
+ */
+int at697pci_init1(struct drvmgr_dev *dev)
+{
+ struct at697pci_priv *priv;
+ struct pci_auto_setup at697pci_auto_cfg;
+
+ DBG("AT697PCI[%d] on bus %s\n", dev->minor_drv,
+ dev->parent->dev->name);
+
+ if ( at697pci_minor != 0 ) {
+ DBG("Driver only supports one PCI core\n");
+ return DRVMGR_FAIL;
+ }
+
+ at697pcipriv = priv = dev->priv;
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ priv->dev = dev;
+ priv->minor = at697pci_minor++;
+
+ if (at697pci_init(priv)) {
+ DBG("Failed to initialize at697pci driver\n");
+ return DRVMGR_FAIL;
+ }
+
+ /* Host is always Big-Endian */
+ pci_endian = PCI_BIG_ENDIAN;
+
+ if (pci_access_drv_register(&at697pci_access_drv)) {
+ /* Access routines registration failed */
+ return DRVMGR_FAIL;
+ }
+
+ /* Prepare memory MAP */
+ at697pci_auto_cfg.options = 0;
+ at697pci_auto_cfg.mem_start = 0;
+ at697pci_auto_cfg.mem_size = 0;
+ at697pci_auto_cfg.memio_start = PCI_MEM_START;
+ at697pci_auto_cfg.memio_size = PCI_MEM_SIZE;
+ at697pci_auto_cfg.io_start = 0;
+ at697pci_auto_cfg.io_size = 0;
+ at697pci_auto_cfg.irq_map = at697pci_bus0_irq_map;
+ at697pci_auto_cfg.irq_route = NULL; /* use standard routing */
+ pci_config_register(&at697pci_auto_cfg);
+
+ if (pci_config_init()) {
+ /* PCI configuration failed */
+ return DRVMGR_FAIL;
+ }
+
+ priv->config.maps_down = &priv->maps_down[0];
+ priv->config.maps_up = &priv->maps_up[0];
+ return pcibus_register(dev, &priv->config);
+}
+
+int at697pci_init2(struct drvmgr_dev *dev)
+{
+#if 0
+ struct at697pci_priv *priv = dev->priv;
+#endif
+ int pin, irq, pio, ioport;
+ LEON_Register_Map *regs = (LEON_Register_Map *)0x80000000;
+
+ /* Enable interrupts now that init1 has been reached for all devices
+ * on the bus.
+ */
+
+ for (pin=1; pin<5; pin++) {
+ irq = at697_pci_irq_table[pin-1];
+ pio = at697_pci_irq_pio_table[pin-1];
+ if ( (pio < 16) && (irq >= 4) && (irq <= 7) ) {
+ /* AT697 I/O IRQ, we know how to set up this
+ *
+ * IRQ 4 -> I/O 0
+ * IRQ 5 -> I/O 1
+ * IRQ 6 -> I/O 2
+ * IRQ 7 -> I/O 3
+ */
+ ioport = irq - 4;
+
+ /* First disable interrupts */
+ regs->PIO_Interrupt &= ~(0xff << (ioport * 8));
+ /* Set PIO as input pin */
+ regs->PIO_Direction &= ~(1 << pio);
+ /* Set Low Level sensitivity */
+ regs->PIO_Interrupt |= ((0x80 | pio) << (ioport * 8));
+ }
+ }
+
+ /* Unmask Interrupt */
+ /*priv->regs->pciite = 0xff;*/
+
+ return DRVMGR_OK;
+}
diff --git a/c/src/lib/libbsp/sparc/leon2/pci/pci.c b/c/src/lib/libbsp/sparc/leon2/pci/pci.c
deleted file mode 100644
index bf1cd32..0000000
--- a/c/src/lib/libbsp/sparc/leon2/pci/pci.c
+++ /dev/null
@@ -1,730 +0,0 @@
-/**
- * @file
- * @ingroup sparc_leon2
- * @brief Basic PCI Io functions
- */
-
-/*
- * pci.c : this file contains basic PCI Io functions.
- *
- * Copyright (C) 1999 valette at crf.canon.fr
- *
- * This code is heavily inspired by the public specification of STREAM V2
- * that can be found at :
- *
- * <http://www.chorus.com/Documentation/index.html> by following
- * the STREAM API Specification Document link.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Till Straumann, <strauman at slac.stanford.edu>, 1/2002
- * - separated bridge detection code out of this file
- *
- * Adapted to LEON2 AT697 PCI
- * Copyright (C) 2006 Gaisler Research
- *
- */
-
-#include <pci.h>
-#include <rtems/bspIo.h>
-#include <stdlib.h>
-
-/* Define PCI_INFO to get a listing of configured devices at boot time */
-#define PCI_INFO 1
-
-/* #define DEBUG 1 */
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-/* allow for overriding these definitions */
-#ifndef PCI_CONFIG_ADDR
-#define PCI_CONFIG_ADDR 0xcf8
-#endif
-#ifndef PCI_CONFIG_DATA
-#define PCI_CONFIG_DATA 0xcfc
-#endif
-
-/* define a shortcut */
-#define pci BSP_pci_configuration
-
-/*
- * Bit encode for PCI_CONFIG_HEADER_TYPE register
- */
-unsigned char ucMaxPCIBus;
-
-typedef struct {
- /* 0x80000100 - PCI Device identification register 1 */
- volatile unsigned int pciid1;
- /* 0x80000104 - PCI Status & Command */
- volatile unsigned int pcisc;
- /* 0x80000108 - PCI Device identification register 2 */
- volatile unsigned int pciid2;
- /* 0x8000010c - BIST, Header type, Cache line size register */
- volatile unsigned int pcibhlc;
- /* 0x80000110 - Memory Base Address Register 1 */
- volatile unsigned int mbar1;
- /* 0x80000114 - Memory Base Address Register 2 */
- volatile unsigned int mbar2;
- /* 0x80000118 - IO Base Address Register 3 */
- volatile unsigned int iobar3;
- /* 0x8000011c - 0x80000128 */
- volatile unsigned int dummy1[4];
- /* 0x8000012c - Subsystem identification register */
- volatile unsigned int pcisid;
- /* 0x80000130 */
- volatile unsigned int dummy2;
- /* 0x80000134 - PCI capabilities pointer register */
- volatile unsigned int pcicp;
- /* 0x80000138 */
- volatile unsigned int dummy3;
- /* 0x8000013c - PCI latency interrupt register */
- volatile unsigned int pcili;
- /* 0x80000140 - PCI retry, trdy config */
- volatile unsigned int pcirt;
- /* 0x80000144 - PCI configuration write register */
- volatile unsigned int pcicw;
- /* 0x80000148 - PCI Initiator Start Address */
- volatile unsigned int pcisa;
- /* 0x8000014c - PCI Initiator Write Register */
- volatile unsigned int pciiw;
- /* 0x80000150 - PCI DMA configuration register */
- volatile unsigned int pcidma;
- /* 0x80000154 - PCI Initiator Status Register */
- volatile unsigned int pciis;
- /* 0x80000158 - PCI Initiator Configuration */
- volatile unsigned int pciic;
- /* 0x8000015c - PCI Target Page Address Register */
- volatile unsigned int pcitpa;
- /* 0x80000160 - PCI Target Status-Command Register */
- volatile unsigned int pcitsc;
- /* 0x80000164 - PCI Interrupt Enable Register */
- volatile unsigned int pciite;
- /* 0x80000168 - PCI Interrupt Pending Register */
- volatile unsigned int pciitp;
- /* 0x8000016c - PCI Interrupt Force Register */
- volatile unsigned int pciitf;
- /* 0x80000170 - PCI Data Register */
- volatile unsigned int pcid;
- /* 0x80000174 - PCI Burst End Register */
- volatile unsigned int pcibe;
- /* 0x80000178 - PCI DMA Address Register */
- volatile unsigned int pcidmaa;
-} AT697_PCI_Map;
-
-AT697_PCI_Map *pcic = (AT697_PCI_Map *) 0x80000100;
-
-#define PCI_MEM_START 0xa0000000
-#define PCI_MEM_END 0xf0000000
-#define PCI_MEM_SIZE (PCI_MEM_START - PCI_MEM_END)
-
-
-struct pci_res {
- unsigned int size;
- unsigned char bar;
- unsigned char devfn;
-};
-
-/* The configuration access functions uses the DMA functionality of the
- * AT697 pci controller to be able access all slots
- */
-
-static int
-BSP_pci_read_config_dword(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, uint32_t *val) {
-
- volatile uint32_t data;
-
- if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f);
- pcic->pcidma = 0xa01;
- pcic->pcidmaa = (unsigned int) &data;
-
- while (pcic->pciitp == 0)
- ;
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- if (pcic->pcisc & 0x20000000) { /* Master Abort */
- pcic->pcisc |= 0x20000000;
- *val = 0xffffffff;
- }
- else
- *val = data;
-
- DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
- bus, slot, function, offset,
- (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), *val);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_read_config_word(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned short *val) {
- uint32_t v;
-
- if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
- *val = 0xffff & (v >> (8*(offset & 3)));
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_read_config_byte(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned char *val) {
- uint32_t v;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- *val = 0xff & (v >> (8*(offset & 3)));
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_write_config_dword(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, uint32_t val) {
-
- if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f);
- pcic->pcidma = 0xb01;
- pcic->pcidmaa = (unsigned int) &val;
-
- while (pcic->pciitp == 0)
- ;
-
- if (pcic->pcisc & 0x20000000) { /* Master Abort */
- pcic->pcisc |= 0x20000000;
- }
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
-/* DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
- bus, slot, function, offset,
- (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), val); */
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_write_config_word(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned short val) {
- uint32_t v;
-
- if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- v = (v & ~(0xffff << (8*(offset&3)))) | ((0xffff&val) << (8*(offset&3)));
-
- return pci_write_config_dword(bus, slot, function, offset&~3, v);
-}
-
-
-static int
-BSP_pci_write_config_byte(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned char val) {
- uint32_t v;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3)));
-
- return pci_write_config_dword(bus, slot, function, offset&~3, v);
-}
-
-
-
-const pci_config_access_functions pci_access_functions = {
- BSP_pci_read_config_byte,
- BSP_pci_read_config_word,
- BSP_pci_read_config_dword,
- BSP_pci_write_config_byte,
- BSP_pci_write_config_word,
- BSP_pci_write_config_dword
-};
-
-rtems_pci_config_t BSP_pci_configuration = {
- (volatile unsigned char*)PCI_CONFIG_ADDR,
- (volatile unsigned char*)PCI_CONFIG_DATA,
- &pci_access_functions
-};
-
-
-static void init_at697_pci(void) {
-
- /* Reset */
- pcic->pciic = 0xffffffff;
-
- /* Map system RAM at pci address 0x40000000
- and system SDRAM to pci address 0x60000000 */
- pcic->mbar1 = 0x40000000;
- pcic->mbar2 = 0x60000000;
- pcic->pcitpa = 0x40006000;
-
- /* Enable PCI master and target memory command response */
- pcic->pcisc |= 0x40 | 0x6;
-
- /* Set latency timer to 64 */
- pcic->pcibhlc = 0x00004000;
-
- /* Set Inititator configuration so that AHB slave accesses
- generate memory read/write commands */
- pcic->pciic = 0x41;
-
- pcic->pciite = 0xff;
-
-}
-
-/* May not pass a 1k boundary */
-static int dma_from_pci_1k(
- unsigned int addr, unsigned int paddr, unsigned char len) {
-
- int retval = 0;
-
- if (addr & 3) {
- return -1;
- }
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- pcic->pcisa = paddr;
- pcic->pcidma = 0xc00 | len;
- pcic->pcidmaa = addr;
-
- while (pcic->pciitp == 0)
- ;
-
- if (pcic->pciitp & 0x7F) {
- retval = -1;
- }
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- if (pcic->pcisc & 0x20000000) { /* Master Abort */
- pcic->pcisc |= 0x20000000;
- retval = -1;
- }
-
- return retval;
-}
-
-/* May not pass a 1k boundary */
-static int dma_to_pci_1k(
- unsigned int addr, unsigned int paddr, unsigned char len) {
-
- int retval = 0;
-
- if (addr & 3) return -1;
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- pcic->pcisa = paddr;
- pcic->pcidma = 0x700 | len;
- pcic->pcidmaa = addr;
-
- while (pcic->pciitp == 0)
- ;
-
- if (pcic->pciitp & 0x7F) retval = -1;
-
- pcic->pciitp = 0xff; /* clear interrupts */
-
- if (pcic->pcisc & 0x20000000) { /* Master Abort */
- pcic->pcisc |= 0x20000000;
- retval = -1;
- }
-
- return retval;
-}
-
-/* Transfer len number of words from addr to paddr */
-int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len) {
-
- int tmp_len;
-
- /* Align to 1k boundary */
- tmp_len = ((addr + 1024) & 0xfffffc00) - addr;
-
- tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4);
-
- if (dma_to_pci_1k(addr, paddr, tmp_len/4) < 0)
- return -1;
-
- addr += tmp_len;
- paddr += tmp_len;
- len -= tmp_len/4;
-
- /* Transfer all 1k blocks */
- while (len >= 128) {
-
- if (dma_to_pci_1k(addr, paddr, 128) < 0)
- return -1;
-
- addr += 512;
- paddr += 512;
- len -= 128;
-
- }
-
- /* Transfer last words */
- if (len) return dma_to_pci_1k(addr, paddr, len);
-
- return 0;
-}
-
-/* Transfer len number of words from paddr to addr */
-int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len) {
-
- int tmp_len;
-
- /* Align to 1k boundary */
- tmp_len = ((addr + 1024) & 0xfffffc00) - addr;
-
- tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4);
-
- if (dma_from_pci_1k(addr, paddr, tmp_len/4) < 0)
- return -1;
-
- addr += tmp_len;
- paddr += tmp_len;
- len -= tmp_len/4;
-
- /* Transfer all 1k blocks */
- while (len >= 128) {
-
- if (dma_from_pci_1k(addr, paddr, 128) < 0)
- return -1;
- addr += 512;
- paddr += 512;
- len -= 128;
-
- }
-
- /* Transfer last words */
- if (len) return dma_from_pci_1k(addr, paddr, len);
-
- return 0;
-}
-
-void pci_mem_enable(unsigned char bus, unsigned char slot,
- unsigned char function) {
- uint32_t data;
-
- pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
- pci_write_config_dword(0, slot, function, PCI_COMMAND,
- data | PCI_COMMAND_MEMORY);
-
-}
-
-void pci_master_enable(unsigned char bus, unsigned char slot,
- unsigned char function) {
- uint32_t data;
-
- pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
- pci_write_config_dword(0, slot, function, PCI_COMMAND,
- data | PCI_COMMAND_MASTER);
-
-}
-
-static inline void swap_res(struct pci_res **p1, struct pci_res **p2) {
-
- struct pci_res *tmp = *p1;
- *p1 = *p2;
- *p2 = tmp;
-
-}
-
-/* pci_allocate_resources
- *
- * This function scans the bus and assigns PCI addresses to all devices. It
- * handles both single function and multi function devices. All allocated
- * devices are enabled and latency timers are set to 40.
- *
- * NOTE that it only allocates PCI memory space devices. IO spaces are
- * not enabled. Also, it does not handle pci-pci bridges. They are left
- * disabled.
- *
- */
-static void pci_allocate_resources(void) {
-
- uint32_t slot, numfuncs, func, id, pos, size, tmp;
- unsigned int i, swapped, addr, dev, fn;
- unsigned char header;
- struct pci_res **res;
-
- res = (struct pci_res **) malloc(sizeof(struct pci_res *)*32*8*6);
-
- for (i = 0; i < 32*8*6; i++) {
- res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));
- res[i]->size = 0;
- res[i]->devfn = i;
- }
-
- for(slot = 0; slot< PCI_MAX_DEVICES; slot++) {
-
- pci_read_config_dword(0, slot, 0, PCI_VENDOR_ID, &id);
-
- if(id == PCI_INVALID_VENDORDEVICEID || id == 0) {
- /*
- * This slot is empty
- */
- continue;
- }
-
- pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
-
- if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) {
- numfuncs = PCI_MAX_FUNCTIONS;
- }
- else {
- numfuncs = 1;
- }
-
- for(func = 0; func < numfuncs; func++) {
-
- pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id);
- if(id == PCI_INVALID_VENDORDEVICEID || id == 0) {
- continue;
- }
-
- pci_read_config_dword(0, slot, func, PCI_CLASS_REVISION, &tmp);
- tmp >>= 16;
- if (tmp == PCI_CLASS_BRIDGE_PCI) {
- continue;
- }
-
- for (pos = 0; pos < 6; pos++) {
- pci_write_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
- pci_read_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), &size);
-
- if (size == 0 || size == 0xffffffff || (size & 0xff) != 0) {
- pci_write_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), 0);
- continue;
- }
-
- else {
- res[slot*8*6+func*6+pos]->size = ~size+1;
- res[slot*8*6+func*6+pos]->devfn = slot*8 + func;
- res[slot*8*6+func*6+pos]->bar = pos;
-
- DBG("Slot: %d, function: %d, bar%d size: %x\n",
- slot, func, pos, ~size+1);
- }
- }
- }
- }
-
-
- /* Sort the resources in descending order */
-
- swapped = 1;
- while (swapped == 1) {
- swapped = 0;
- for (i = 0; i < 32*8*6-1; i++) {
- if (res[i]->size < res[i+1]->size) {
- swap_res(&res[i], &res[i+1]);
- swapped = 1;
- }
- }
- i++;
- }
-
- /* Assign the BARs */
-
- addr = PCI_MEM_START;
- for (i = 0; i < 32*8*6; i++) {
-
- if (res[i]->size == 0) {
- goto done;
- }
- if ( (addr + res[i]->size) > PCI_MEM_END) {
- printk("Out of PCI memory space, all devices not configured.\n");
- goto done;
- }
-
- dev = res[i]->devfn >> 3;
- fn = res[i]->devfn & 7;
-
- DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n",
- addr, dev, fn, res[i]->bar);
- pci_write_config_dword(0, dev, fn,
- PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
- addr += res[i]->size;
-
- /* Set latency timer to 64 */
- pci_read_config_dword(0, dev, fn, 0xC, &tmp);
- pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000);
-
- pci_mem_enable(0, dev, fn);
-
- }
-
-
-
-done:
-
-#ifdef PCI_INFO
- printk("\nPCI devices found and configured:\n");
- for (slot = 0; slot < PCI_MAX_DEVICES; slot++) {
-
- pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
-
- if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) {
- numfuncs = PCI_MAX_FUNCTIONS;
- }
- else {
- numfuncs = 1;
- }
-
- for (func = 0; func < numfuncs; func++) {
-
- pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp);
-
- if (tmp & PCI_COMMAND_MEMORY) {
-
- pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id);
-
- if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
-
- printk("\nSlot %d function: %d\nVendor id: 0x%x, "
- "device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
-
- for (pos = 0; pos < 6; pos++) {
- pci_read_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + pos*4, &tmp);
-
- if (tmp != 0 && tmp != 0xffffffff && (tmp & 0xff) == 0) {
-
- printk("\tBAR %d: %x\n", pos, tmp);
- }
-
- }
- printk("\n");
-
- }
-
- }
- }
- printk("\n");
-#endif
-
- for (i = 0; i < 1536; i++) {
- free(res[i]);
- }
- free(res);
-}
-
-
-
-
-
-
-
-/*
- * This routine determines the maximum bus number in the system
- */
-int init_pci(void)
-{
- unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs;
- unsigned char ucHeader;
- unsigned char ucMaxSubordinate;
- uint32_t ulClass, ulDeviceID;
-
- init_at697_pci();
- pci_allocate_resources();
-
-/*
- * Scan PCI bus 0 looking for PCI-PCI bridges
- */
- for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- 0,
- PCI_VENDOR_ID,
- &ulDeviceID);
- if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
-/*
- * This slot is empty
- */
- continue;
- }
- (void)pci_read_config_byte(0,
- ucSlotNumber,
- 0,
- PCI_HEADER_TYPE,
- &ucHeader);
- if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION) {
- ucNumFuncs=PCI_MAX_FUNCTIONS;
- }
- else {
- ucNumFuncs=1;
- }
- for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) {
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_VENDOR_ID,
- &ulDeviceID);
- if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
-/*
- * This slot/function is empty
- */
- continue;
- }
-
-/*
- * This slot/function has a device fitted.
- */
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_CLASS_REVISION,
- &ulClass);
- ulClass >>= 16;
- if (ulClass == PCI_CLASS_BRIDGE_PCI) {
-/*
- * We have found a PCI-PCI bridge
- */
- (void)pci_read_config_byte(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_SUBORDINATE_BUS,
- &ucMaxSubordinate);
- if(ucMaxSubordinate>ucMaxPCIBus) {
- ucMaxPCIBus=ucMaxSubordinate;
- }
- }
- }
- }
- return 0;
-}
-
-/*
- * Return the number of PCI busses in the system
- */
-unsigned char BusCountPCI(void)
-{
- return(ucMaxPCIBus+1);
-}
diff --git a/c/src/lib/libbsp/sparc/leon2/preinstall.am b/c/src/lib/libbsp/sparc/leon2/preinstall.am
index 10a0bbc..01b2ab9 100644
--- a/c/src/lib/libbsp/sparc/leon2/preinstall.am
+++ b/c/src/lib/libbsp/sparc/leon2/preinstall.am
@@ -109,10 +109,6 @@ $(PROJECT_INCLUDE)/debug_defs.h: ../../sparc/shared/include/debug_defs.h $(PROJE
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/debug_defs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/debug_defs.h
-$(PROJECT_INCLUDE)/pci.h: ../../sparc/shared/include/pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci.h
-
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am
index f263ab6..a451208 100644
--- a/c/src/lib/libbsp/sparc/leon3/Makefile.am
+++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am
@@ -100,9 +100,14 @@ libbsp_a_SOURCES += \
../../shared/src/irq-legacy.c \
../../shared/src/irq-server.c \
../../shared/src/irq-shell.c
+
# PCI
-include_HEADERS += ../../sparc/shared/include/pci.h
-libbsp_a_SOURCES += pci/pci.c ../../sparc/shared/pci/pcifinddevice.c
+include_HEADERS += ../../sparc/shared/include/grpci2.h
+libbsp_a_SOURCES += ../../sparc/shared/pci/grpci.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pcif.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_le.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c
# B1553BRM
include_HEADERS += ../../sparc/shared/include/b1553brm.h \
diff --git a/c/src/lib/libbsp/sparc/leon3/pci/pci.c b/c/src/lib/libbsp/sparc/leon3/pci/pci.c
deleted file mode 100644
index 5e95cbc..0000000
--- a/c/src/lib/libbsp/sparc/leon3/pci/pci.c
+++ /dev/null
@@ -1,613 +0,0 @@
-/*
- * pci.c : this file contains basic PCI Io functions.
- *
- * Copyright (C) 1999 valette at crf.canon.fr
- *
- * This code is heavily inspired by the public specification of STREAM V2
- * that can be found at :
- *
- * <http://www.chorus.com/Documentation/index.html> by following
- * the STREAM API Specification Document link.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Till Straumann, <strauman at slac.stanford.edu>, 1/2002
- * - separated bridge detection code out of this file
- *
- *
- * Adapted to GRPCI
- * Copyright (C) 2006 Gaisler Research
- *
- */
-
-#include <pci.h>
-#include <stdlib.h>
-#include <rtems/bspIo.h>
-
-#define PCI_ADDR 0x80000400
-#define DMAPCI_ADDR 0x80000500
-#define PCI_CONF 0xfff50000
-#define PCI_MEM_START 0xe0000000
-#define PCI_MEM_END 0xf0000000
-#define PCI_MEM_SIZE (PCI_MEM_START - PCI_MEM_END)
-
-/* If uncommented byte twisting is enabled */
-/*#define BT_ENABLED 1*/
-
-/* Define PCI_INFO to get a listing of configured devices at boot time */
-#define PCI_INFO 1
-
-#define DEBUG 1
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-/* allow for overriding these definitions */
-#ifndef PCI_CONFIG_ADDR
-#define PCI_CONFIG_ADDR 0xcf8
-#endif
-#ifndef PCI_CONFIG_DATA
-#define PCI_CONFIG_DATA 0xcfc
-#endif
-
-/* define a shortcut */
-#define pci BSP_pci_configuration
-
-/*
- * Bit encode for PCI_CONFIG_HEADER_TYPE register
- */
-unsigned char ucMaxPCIBus;
-typedef struct {
- volatile unsigned int cfg_stat;
- volatile unsigned int bar0;
- volatile unsigned int page0;
- volatile unsigned int bar1;
- volatile unsigned int page1;
- volatile unsigned int iomap;
- volatile unsigned int stat_cmd;
-} LEON3_GRPCI_Regs_Map;
-
-LEON3_GRPCI_Regs_Map *pcic = (LEON3_GRPCI_Regs_Map *) PCI_ADDR;
-unsigned int *pcidma = (unsigned int *)DMAPCI_ADDR;
-
-struct pci_res {
- unsigned int size;
- unsigned char bar;
- unsigned char devfn;
-};
-
-static inline unsigned int flip_dword (unsigned int l)
-{
- return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) |
- (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
-}
-
-
-/* The configuration access functions uses the DMA functionality of the
- * AT697 pci controller to be able access all slots
- */
-
-
-static int
-BSP_pci_read_config_dword(
- unsigned char bus,
- unsigned char slot,
- unsigned char function,
- unsigned char offset,
- uint32_t *val
-)
-{
- volatile unsigned int *pci_conf;
-
- if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- if (slot > 21) {
- *val = 0xffffffff;
- return PCIBIOS_SUCCESSFUL;
- }
-
- pci_conf = (volatile unsigned int *) (PCI_CONF +
- ((slot<<11) | (function<<8) | offset));
-
-#ifdef BT_ENABLED
- *val = flip_dword(*pci_conf);
-#else
- *val = *pci_conf;
-#endif
-
- if (pcic->cfg_stat & 0x100) {
- *val = 0xffffffff;
- }
-
- DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
- bus, slot, function, offset,
- (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), *val);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_read_config_word(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned short *val) {
- uint32_t v;
-
- if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
- *val = 0xffff & (v >> (8*(offset & 3)));
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_read_config_byte(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned char *val) {
- uint32_t v;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- *val = 0xff & (v >> (8*(offset & 3)));
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_write_config_dword(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, uint32_t val) {
-
- volatile unsigned int *pci_conf;
- unsigned int value;
-
- if (offset & 3 || bus != 0) return PCIBIOS_BAD_REGISTER_NUMBER;
-
-
- pci_conf = (volatile unsigned int *) (PCI_CONF +
- ((slot<<11) | (function<<8) | (offset & ~3)));
-
-#ifdef BT_ENABLED
- value = flip_dword(val);
-#else
- value = val;
-#endif
-
- *pci_conf = value;
-
- DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
- bus, slot, function, offset,
- (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), value);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int
-BSP_pci_write_config_word(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned short val) {
- uint32_t v;
-
- if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- v = (v & ~(0xffff << (8*(offset&3)))) | ((0xffff&val) << (8*(offset&3)));
-
- return pci_write_config_dword(bus, slot, function, offset&~3, v);
-}
-
-
-static int
-BSP_pci_write_config_byte(unsigned char bus, unsigned char slot,
- unsigned char function, unsigned char offset, unsigned char val) {
- uint32_t v;
-
- pci_read_config_dword(bus, slot, function, offset&~3, &v);
-
- v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3)));
-
- return pci_write_config_dword(bus, slot, function, offset&~3, v);
-}
-
-
-
-const pci_config_access_functions pci_access_functions = {
- BSP_pci_read_config_byte,
- BSP_pci_read_config_word,
- BSP_pci_read_config_dword,
- BSP_pci_write_config_byte,
- BSP_pci_write_config_word,
- BSP_pci_write_config_dword
-};
-
-rtems_pci_config_t BSP_pci_configuration = {
- (volatile unsigned char*)PCI_CONFIG_ADDR,
- (volatile unsigned char*)PCI_CONFIG_DATA,
- &pci_access_functions
-};
-
-
-static int init_grpci(void) {
-
- volatile unsigned int *page0 = (unsigned volatile int *) PCI_MEM_START;
- uint32_t data;
-#ifndef BT_ENABLED
- uint32_t addr;
-#endif
-
-#ifndef BT_ENABLED
- pci_write_config_dword(0,0,0,0x10, 0xffffffff);
- pci_read_config_dword(0,0,0,0x10, &addr);
- /* Setup bar0 to nonzero value (grpci considers BAR==0 as invalid) */
- pci_write_config_dword(0,0,0,0x10, flip_dword(0x10000000));
- /* page0 is accessed through upper half of bar0 */
- addr = (~flip_dword(addr)+1)>>1;
- /* Setup mmap reg so we can reach bar0 */
- pcic->cfg_stat |= 0x10000000;
- /* Disable bytetwisting ... */
- page0[addr/4] = 0;
-#endif
-
- /* set 1:1 mapping between AHB -> PCI memory */
- pcic->cfg_stat = (pcic->cfg_stat & 0x0fffffff) | PCI_MEM_START;
-
- /* and map system RAM at pci address 0x40000000 */
- pci_write_config_dword(0, 0, 0, 0x14, 0x40000000);
- pcic->page1 = 0x40000000;
-
- /* set as bus master and enable pci memory responses */
- pci_read_config_dword(0, 0, 0, 0x4, &data);
- pci_write_config_dword(0, 0, 0, 0x4, data | 0x6);
-
- return 0;
-}
-
-/* DMA functions which uses GRPCIs optional DMA controller (len in words) */
-int dma_to_pci(unsigned int ahb_addr, unsigned int pci_addr,
- unsigned int len) {
- int ret = 0;
-
- pcidma[0] = 0x82;
- pcidma[1] = ahb_addr;
- pcidma[2] = pci_addr;
- pcidma[3] = len;
- pcidma[0] = 0x83;
-
- while ( (pcidma[0] & 0x4) == 0)
- ;
-
- if (pcidma[0] & 0x8) { /* error */
- ret = -1;
- }
-
- pcidma[0] |= 0xC;
- return ret;
-
-}
-
-int dma_from_pci(unsigned int ahb_addr, unsigned int pci_addr,
- unsigned int len) {
- int ret = 0;
-
- pcidma[0] = 0x80;
- pcidma[1] = ahb_addr;
- pcidma[2] = pci_addr;
- pcidma[3] = len;
- pcidma[0] = 0x81;
-
- while ( (pcidma[0] & 0x4) == 0)
- ;
-
- if (pcidma[0] & 0x8) { /* error */
- ret = -1;
- }
-
- pcidma[0] |= 0xC;
- return ret;
-
-}
-
-
-void pci_mem_enable(unsigned char bus, unsigned char slot,
- unsigned char function) {
- uint32_t data;
-
- pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
- pci_write_config_dword(0, slot, function, PCI_COMMAND,
- data | PCI_COMMAND_MEMORY);
-
-}
-
-void pci_master_enable(unsigned char bus, unsigned char slot,
- unsigned char function) {
- uint32_t data;
-
- pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
- pci_write_config_dword(0, slot, function, PCI_COMMAND,
- data | PCI_COMMAND_MASTER);
-
-}
-
-static inline void swap_res(struct pci_res **p1, struct pci_res **p2) {
-
- struct pci_res *tmp = *p1;
- *p1 = *p2;
- *p2 = tmp;
-
-}
-
-/* pci_allocate_resources
- *
- * This function scans the bus and assigns PCI addresses to all devices.
- * It handles both single function and multi function devices. All
- * allocated devices are enabled and latency timers are set to 40.
- *
- * NOTE that it only allocates PCI memory space devices (that are at
- * least 1 KB). IO spaces are not enabled. Also, it does not handle
- * pci-pci bridges. They are left disabled.
- *
-*/
-static void pci_allocate_resources(void) {
-
- unsigned int slot, numfuncs, func, pos, i, swapped, addr, dev, fn;
- uint32_t id, tmp, size;
- unsigned char header;
- struct pci_res **res;
-
- res = (struct pci_res **) malloc(sizeof(struct pci_res *)*32*8*6);
-
- for (i = 0; i < 32*8*6; i++) {
- res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));
- res[i]->size = 0;
- res[i]->devfn = i;
- }
-
- for(slot = 1; slot < PCI_MAX_DEVICES; slot++) {
-
- pci_read_config_dword(0, slot, 0, PCI_VENDOR_ID, &id);
-
- if(id == PCI_INVALID_VENDORDEVICEID || id == 0) {
- /*
- * This slot is empty
- */
- continue;
- }
-
- pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
-
- if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) {
- numfuncs = PCI_MAX_FUNCTIONS;
- }
- else {
- numfuncs = 1;
- }
-
- for(func = 0; func < numfuncs; func++) {
-
- pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id);
- if(id == PCI_INVALID_VENDORDEVICEID || id == 0) {
- continue;
- }
-
- pci_read_config_dword(0, slot, func, PCI_CLASS_REVISION, &tmp);
- tmp >>= 16;
- if (tmp == PCI_CLASS_BRIDGE_PCI) {
- continue;
- }
-
- for (pos = 0; pos < 6; pos++) {
- pci_write_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
- pci_read_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), &size);
-
- if (size == 0 || size == 0xffffffff || (size & 0x3f1) != 0){
- pci_write_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + (pos<<2), 0);
- continue;
-
- }else {
- size &= 0xfffffff0;
- res[slot*8*6+func*6+pos]->size = ~size+1;
- res[slot*8*6+func*6+pos]->devfn = slot*8 + func;
- res[slot*8*6+func*6+pos]->bar = pos;
-
- DBG("Slot: %d, function: %d, bar%d size: %x\n",
- slot, func, pos, ~size+1);
- }
- }
- }
- }
-
-
- /* Sort the resources in descending order */
- swapped = 1;
- while (swapped == 1) {
- swapped = 0;
- for (i = 0; i < 32*8*6-1; i++) {
- if (res[i]->size < res[i+1]->size) {
- swap_res(&res[i], &res[i+1]);
- swapped = 1;
- }
- }
- i++;
- }
-
- /* Assign the BARs */
- addr = PCI_MEM_START;
- for (i = 0; i < 32*8*6; i++) {
-
- if (res[i]->size == 0) {
- goto done;
- }
- if ( (addr + res[i]->size) > PCI_MEM_END) {
- printk("Out of PCI memory space, all devices not configured.\n");
- goto done;
- }
-
- dev = res[i]->devfn >> 3;
- fn = res[i]->devfn & 7;
-
- DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n",
- addr, dev, fn, res[i]->bar);
- pci_write_config_dword(0, dev, fn,
- PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
- addr += res[i]->size;
-
- /* Set latency timer to 64 */
- pci_read_config_dword(0, dev, fn, 0xC, &tmp);
- pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000);
-
- pci_mem_enable(0, dev, fn);
-
- }
-
-
-
-done:
-
-#ifdef PCI_INFO
- printk("\nPCI devices found and configured:\n");
- for (slot = 1; slot < PCI_MAX_DEVICES; slot++) {
-
- pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
-
- if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) {
- numfuncs = PCI_MAX_FUNCTIONS;
- }
- else {
- numfuncs = 1;
- }
-
- for (func = 0; func < numfuncs; func++) {
-
- pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp);
-
- if (tmp & PCI_COMMAND_MEMORY) {
-
- pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id);
-
- if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
-
- printk("\nSlot %d function: %d\nVendor id: 0x%x, "
- "device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
-
- for (pos = 0; pos < 6; pos++) {
- pci_read_config_dword(0, slot, func,
- PCI_BASE_ADDRESS_0 + pos*4, &tmp);
-
- if (tmp != 0 && tmp != 0xffffffff && (tmp & 0x3f1) == 0) {
-
- printk("\tBAR %d: %x\n", pos, tmp);
- }
-
- }
- printk("\n");
-
- }
-
- }
- }
- printk("\n");
-#endif
-
- for (i = 0; i < 1536; i++) {
- free(res[i]);
- }
- free(res);
-}
-
-
-
-int init_pci(void)
-{
- unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs;
- unsigned char ucHeader;
- unsigned char ucMaxSubordinate;
- uint32_t ulClass, ulDeviceID;
-
- DBG("Initializing PCI\n");
- if ( init_grpci() ) {
- return -1;
- }
- pci_allocate_resources();
- DBG("PCI resource allocation done\n");
-/*
- * Scan PCI bus 0 looking for PCI-PCI bridges
- */
- for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- 0,
- PCI_VENDOR_ID,
- &ulDeviceID);
- if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
-/*
- * This slot is empty
- */
- continue;
- }
- (void)pci_read_config_byte(0,
- ucSlotNumber,
- 0,
- PCI_HEADER_TYPE,
- &ucHeader);
- if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION) {
- ucNumFuncs=PCI_MAX_FUNCTIONS;
- }
- else {
- ucNumFuncs=1;
- }
- for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) {
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_VENDOR_ID,
- &ulDeviceID);
- if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
-/*
- * This slot/function is empty
- */
- continue;
- }
-
-/*
- * This slot/function has a device fitted.
- */
- (void)pci_read_config_dword(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_CLASS_REVISION,
- &ulClass);
- ulClass >>= 16;
- if (ulClass == PCI_CLASS_BRIDGE_PCI) {
-/*
- * We have found a PCI-PCI bridge
- */
- (void)pci_read_config_byte(0,
- ucSlotNumber,
- ucFnNumber,
- PCI_SUBORDINATE_BUS,
- &ucMaxSubordinate);
- if(ucMaxSubordinate>ucMaxPCIBus) {
- ucMaxPCIBus=ucMaxSubordinate;
- }
- }
- }
- }
- return 0;
-}
-
-/*
- * Return the number of PCI busses in the system
- */
-unsigned char BusCountPCI(void)
-{
- return(ucMaxPCIBus+1);
-}
diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am
index a45fc31..a12563a 100644
--- a/c/src/lib/libbsp/sparc/leon3/preinstall.am
+++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am
@@ -125,9 +125,9 @@ $(PROJECT_INCLUDE)/bsp/irq.h: include/bsp/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstam
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
-$(PROJECT_INCLUDE)/pci.h: ../../sparc/shared/include/pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci.h
+$(PROJECT_INCLUDE)/grpci2.h: ../../sparc/shared/include/grpci2.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grpci2.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/grpci2.h
$(PROJECT_INCLUDE)/b1553brm.h: ../../sparc/shared/include/b1553brm.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm.h
diff --git a/c/src/lib/libbsp/sparc/shared/include/grpci2.h b/c/src/lib/libbsp/sparc/shared/include/grpci2.h
new file mode 100644
index 0000000..6316c7a
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/grpci2.h
@@ -0,0 +1,61 @@
+/* GRLIB GRPCI2 PCI HOST driver.
+ *
+ * COPYRIGHT (c) 2011
+ * Cobham Gaisler AB.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GRPCI2_H__
+#define __GRPCI2_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void grpci2_register_drv(void);
+
+/* Driver Resources:
+ *
+ * PCI Interrupts
+ * ==============
+ * The interrupt settings are normally autodetected from Plyg&Play, however
+ * if IRQs are routed using custom GPIO pins in order to reduce the PIN count
+ * reserved for PCI, the options below can be used to tell GRPCI2 driver which
+ * System IRQ a PCI interrupt is connected to.
+ * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to
+ * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to
+ * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to
+ * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to
+ *
+ * Name="IRQmask", Type=INT,
+ *
+ * PCI Bytetwisting (endianess)
+ * ============================
+ * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware
+ *
+ * PCI Host's Target BARs setup
+ * ============================
+ * The Host's BARs are not configured by the configuration routines, by default
+ * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to
+ * the Main Memory for the Host.
+ * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host
+ */
+
+/* When the Host acts as a target on the PCI bus, the PCI BARs of the host's
+ * configuration space determine at which PCI address the Host will be accessed
+ * at and when accessing a BAR which AMBA address it will be translated to.
+ */
+struct grpci2_pcibar_cfg {
+ unsigned int pciadr; /* PCI address of BAR (BAR content) */
+ unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */
+ unsigned int barsize; /* PCI BAR Size, must be a power of 2 */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/pci.h b/c/src/lib/libbsp/sparc/shared/include/pci.h
deleted file mode 100644
index bb7afd2..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/pci.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/**
- * @file
- * @ingroup sparc_bsp
- * @defgroup pci PCI
- * @ingroup pci
- * @brief PCI defines and function prototypes
- */
-
-/*
- * Copyright 1994, Drew Eckhardt
- * Copyright 1997, 1998 Martin Mares <mj at atrey.karlin.mff.cuni.cz>
- *
- * For more information, please consult the following manuals (look at
- * http://www.pcisig.com/ for how to get them):
- *
- * PCI BIOS Specification
- * PCI Local Bus Specification
- * PCI to PCI Bridge Specification
- * PCI System Design Guide
- */
-
-#ifndef RTEMS_PCI_H
-#define RTEMS_PCI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/pci.h>
-
-/*
- * Return the number of PCI busses in the system
- */
-extern unsigned char BusCountPCI(void);
-extern int init_pci(void);
-
-extern int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len);
-extern int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len);
-extern void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function);
-extern void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function);
-
-/* scan for a specific device */
-/* find a particular PCI device
- * (currently, only bus0 is scanned for device/fun0)
- *
- * RETURNS: zero on success, bus/dev/fun in *pbus / *pdev / *pfun
- */
-int
-BSP_pciFindDevice(unsigned short vendorid, unsigned short deviceid,
- int instance, int *pbus, int *pdev, int *pfun);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* RTEMS_PCI_H */
diff --git a/c/src/lib/libbsp/sparc/shared/pci/grpci.c b/c/src/lib/libbsp/sparc/shared/pci/grpci.c
new file mode 100644
index 0000000..f496405
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/grpci.c
@@ -0,0 +1,687 @@
+/* GRLIB GRPCI PCI HOST driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GRPCI core and initialize,
+ * - the PCI Library (pci.c)
+ * - the general part of the PCI Bus driver (pci_bus.c)
+ *
+ * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
+ * default taken from Plug and Play, but may be overridden by the
+ * driver resources INTA#..INTD#.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <rtems/bspIo.h>
+#include <libcpu/byteorder.h>
+#include <libcpu/access.h>
+#include <pci.h>
+#include <pci/cfg.h>
+
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <ambapp.h>
+#include <drvmgr/pci_bus.h>
+
+#define DMAPCI_ADDR 0x80000500
+
+/* Configuration options */
+#define SYSTEM_MAINMEM_START 0x40000000
+
+/* If defined to 1 - byte twisting is enabled by default */
+#define DEFAULT_BT_ENABLED 0
+
+/* Interrupt assignment. Set to other value than 0xff in order to
+ * override defaults and plug&play information
+ */
+#ifndef GRPCI_INTA_SYSIRQ
+ #define GRPCI_INTA_SYSIRQ 0xff
+#endif
+#ifndef GRPCI_INTB_SYSIRQ
+ #define GRPCI_INTB_SYSIRQ 0xff
+#endif
+#ifndef GRPCI_INTC_SYSIRQ
+ #define GRPCI_INTC_SYSIRQ 0xff
+#endif
+#ifndef GRPCI_INTD_SYSIRQ
+ #define GRPCI_INTD_SYSIRQ 0xff
+#endif
+
+#define PAGE0_BTEN_BIT 0
+#define PAGE0_BTEN (1<<PAGE0_BTEN_BIT)
+
+#define CFGSTAT_HOST_BIT 13
+#define CFGSTAT_HOST (1<<CFGSTAT_HOST_BIT)
+
+/*#define DEBUG 1*/
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define PCI_INVALID_VENDORDEVICEID 0xffffffff
+#define PCI_MULTI_FUNCTION 0x80
+
+/*
+ * Bit encode for PCI_CONFIG_HEADER_TYPE register
+ */
+struct grpci_regs {
+ volatile unsigned int cfg_stat;
+ volatile unsigned int bar0;
+ volatile unsigned int page0;
+ volatile unsigned int bar1;
+ volatile unsigned int page1;
+ volatile unsigned int iomap;
+ volatile unsigned int stat_cmd;
+ volatile unsigned int irq;
+};
+
+struct grpci_priv *grpcipriv = NULL;
+static int grpci_minor = 0;
+static unsigned int *pcidma = (unsigned int *)DMAPCI_ADDR;
+
+/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
+ * to a system interrupt number.
+ */
+unsigned char grpci_pci_irq_table[4] =
+{
+ /* INTA# */ GRPCI_INTA_SYSIRQ,
+ /* INTB# */ GRPCI_INTB_SYSIRQ,
+ /* INTC# */ GRPCI_INTC_SYSIRQ,
+ /* INTD# */ GRPCI_INTD_SYSIRQ
+};
+
+/* Driver private data struture */
+struct grpci_priv {
+ struct drvmgr_dev *dev;
+ struct grpci_regs *regs;
+ int irq;
+ int minor;
+
+ uint32_t bar1_pci_adr;
+ uint32_t bar1_size;
+
+ int bt_enabled;
+ unsigned int pci_area;
+ unsigned int pci_area_end;
+ unsigned int pci_io;
+ unsigned int pci_conf;
+ unsigned int pci_conf_end;
+
+ uint32_t devVend; /* Host PCI Vendor/Device ID */
+
+ struct drvmgr_map_entry maps_up[2];
+ struct drvmgr_map_entry maps_down[2];
+ struct pcibus_config config;
+};
+
+int grpci_init1(struct drvmgr_dev *dev);
+
+/* GRPCI DRIVER */
+
+struct drvmgr_drv_ops grpci_ops =
+{
+ .init = {grpci_init1, NULL, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct amba_dev_id grpci_ids[] =
+{
+ {VENDOR_GAISLER, GAISLER_PCIFBRG},
+ {0, 0} /* Mark end of table */
+};
+
+struct amba_drv_info grpci_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_AMBAPP_GAISLER_GRPCI_ID, /* Driver ID */
+ "GRPCI_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
+ &grpci_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct grpci_priv), /* Make drvmgr alloc private */
+ },
+ &grpci_ids[0]
+};
+
+void grpci_register_drv(void)
+{
+ DBG("Registering GRPCI driver\n");
+ drvmgr_drv_register(&grpci_info.general);
+}
+
+int grpci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
+{
+ struct grpci_priv *priv = grpcipriv;
+ volatile uint32_t *pci_conf;
+ unsigned int devfn = PCI_DEV_DEVFUNC(dev);
+ int retval;
+ int bus = PCI_DEV_BUS(dev);
+
+ if (ofs & 3)
+ return PCISTS_EINVAL;
+
+ if (PCI_DEV_SLOT(dev) > 21) {
+ *val = 0xffffffff;
+ return PCISTS_OK;
+ }
+
+ /* Select bus */
+ priv->regs->cfg_stat = (priv->regs->cfg_stat & ~(0xf<<23)) | (bus<<23);
+
+ pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs);
+
+ if (priv->bt_enabled) {
+ *val = CPU_swap_u32(*pci_conf);
+ } else {
+ *val = *pci_conf;
+ }
+
+ if (priv->regs->cfg_stat & 0x100) {
+ *val = 0xffffffff;
+ retval = PCISTS_MSTABRT;
+ } else
+ retval = PCISTS_OK;
+
+ DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, *val);
+
+ return retval;
+}
+
+
+int grpci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = grpci_cfg_r32(dev, ofs & ~0x3, &v);
+ *val = 0xffff & (v >> (8*(ofs & 0x3)));
+
+ return retval;
+}
+
+int grpci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = grpci_cfg_r32(dev, ofs & ~0x3, &v);
+
+ *val = 0xff & (v >> (8*(ofs & 3)));
+
+ return retval;
+}
+
+int grpci_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
+{
+ struct grpci_priv *priv = grpcipriv;
+ volatile uint32_t *pci_conf;
+ uint32_t value, devfn = PCI_DEV_DEVFUNC(dev);
+ int bus = PCI_DEV_BUS(dev);
+
+ if (ofs & 0x3)
+ return PCISTS_EINVAL;
+
+ if (PCI_DEV_SLOT(dev) > 21)
+ return PCISTS_MSTABRT;
+
+ /* Select bus */
+ priv->regs->cfg_stat = (priv->regs->cfg_stat & ~(0xf<<23)) | (bus<<23);
+
+ pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs);
+
+ if ( priv->bt_enabled ) {
+ value = CPU_swap_u32(val);
+ } else {
+ value = val;
+ }
+
+ *pci_conf = value;
+
+ DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, value);
+
+ return PCISTS_OK;
+}
+
+int grpci_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = grpci_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
+
+ return grpci_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+int grpci_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = grpci_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
+
+ return grpci_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+/* Return the assigned system IRQ number that corresponds to the PCI
+ * "Interrupt Pin" information from configuration space.
+ *
+ * The IRQ information is stored in the grpci_pci_irq_table configurable
+ * by the user.
+ *
+ * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
+ * 0xff if not assigned.
+ */
+uint8_t grpci_bus0_irq_map(pci_dev_t dev, int irq_pin)
+{
+ uint8_t sysIrqNr = 0; /* not assigned */
+ int irq_group;
+
+ if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
+ /* Use default IRQ decoding on PCI BUS0 according slot numbering */
+ irq_group = PCI_DEV_SLOT(dev) & 0x3;
+ irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
+ /* Valid PCI "Interrupt Pin" number */
+ sysIrqNr = grpci_pci_irq_table[irq_pin];
+ }
+ return sysIrqNr;
+}
+
+int grpci_translate(uint32_t *address, int type, int dir)
+{
+ uint32_t adr;
+ struct grpci_priv *priv = grpcipriv;
+
+ if (type == 1) {
+ /* I/O */
+ if (dir != 0) {
+ /* The PCI bus can not access the CPU bus from I/O
+ * because GRPCI core does not support I/O BARs
+ */
+ return -1;
+ }
+
+ /* We have got a PCI BAR address that the CPU want to access...
+ * Check that it is within the PCI I/O window, I/O adresses
+ * are mapped 1:1 with GRPCI driver... no translation needed.
+ */
+ adr = *(uint32_t *)address;
+ if (adr < priv->pci_io || adr >= priv->pci_conf)
+ return -1;
+ } else {
+ /* MEMIO and MEM.
+ * Memory space is mapped 1:1 so no translation is needed.
+ * Check that address is within accessible windows.
+ */
+ adr = *(uint32_t *)address;
+ if (dir == 0) {
+ /* PCI BAR to AMBA-CPU address.. check that it is
+ * located within GRPCI PCI Memory Window
+ * adr = PCI address.
+ */
+ if (adr < priv->pci_area || adr >= priv->pci_area_end)
+ return -1;
+ } else {
+ /* We have a CPU address and want to get access to it
+ * from PCI space, typically when doing DMA into CPU
+ * RAM. The GRPCI core has two target BARs that PCI
+ * masters can access, we check here that the address
+ * is accessible from PCI.
+ * adr = AMBA address.
+ */
+ if (adr < priv->bar1_pci_adr ||
+ adr >= (priv->bar1_pci_adr + priv->bar1_size))
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
+extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
+
+/* GRPCI PCI access routines, default to Little-endian PCI Bus */
+struct pci_access_drv grpci_access_drv = {
+ .cfg =
+ {
+ grpci_cfg_r8,
+ grpci_cfg_r16,
+ grpci_cfg_r32,
+ grpci_cfg_w8,
+ grpci_cfg_w16,
+ grpci_cfg_w32,
+ },
+ .io =
+ {
+ _ld8,
+ _ld_le16,
+ _ld_le32,
+ _st8,
+ _st_le16,
+ _st_le32,
+ },
+ .memreg = &pci_memreg_sparc_le_ops,
+ .translate = grpci_translate,
+};
+
+struct pci_io_ops grpci_io_ops_be =
+{
+ _ld8,
+ _ld_be16,
+ _ld_be32,
+ _st8,
+ _st_be16,
+ _st_be32,
+};
+
+int grpci_hw_init(struct grpci_priv *priv)
+{
+ volatile unsigned int *mbar0, *page0;
+ uint32_t data, addr, mbar0size;
+ pci_dev_t host = PCI_DEV(0, 0, 0);
+
+ mbar0 = (volatile unsigned int *)priv->pci_area;
+
+ if ( !priv->bt_enabled && ((priv->regs->page0 & PAGE0_BTEN) == PAGE0_BTEN) ) {
+ /* Byte twisting is on, turn it off */
+ grpci_cfg_w32(host, PCI_BASE_ADDRESS_0, 0xffffffff);
+ grpci_cfg_r32(host, PCI_BASE_ADDRESS_0, &addr);
+ /* Setup bar0 to nonzero value */
+ grpci_cfg_w32(host, PCI_BASE_ADDRESS_0,
+ CPU_swap_u32(0x80000000));
+ /* page0 is accessed through upper half of bar0 */
+ addr = (~CPU_swap_u32(addr)+1)>>1;
+ mbar0size = addr*2;
+ DBG("GRPCI: Size of MBAR0: 0x%x, MBAR0: 0x%x(lower) 0x%x(upper)\n",mbar0size,((unsigned int)mbar0),((unsigned int)mbar0)+mbar0size/2);
+ page0 = &mbar0[mbar0size/8];
+ DBG("GRPCI: PAGE0 reg address: 0x%x (0x%x)\n",((unsigned int)mbar0)+mbar0size/2,page0);
+ priv->regs->cfg_stat = (priv->regs->cfg_stat & (~0xf0000000)) | 0x80000000; /* Setup mmap reg so we can reach bar0 */
+ *page0 = 0<<PAGE0_BTEN_BIT; /* Disable bytetwisting ... */
+ }
+
+ /* Get the GRPCI Host PCI ID */
+ grpci_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+
+ /* set 1:1 mapping between AHB -> PCI memory */
+ priv->regs->cfg_stat = (priv->regs->cfg_stat & 0x0fffffff) | priv->pci_area;
+
+ /* determine size of target BAR1 */
+ grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
+ grpci_cfg_r32(host, PCI_BASE_ADDRESS_1, &addr);
+ priv->bar1_size = (~(addr & ~0xf)) + 1;
+
+ /* and map system RAM at pci address 0x40000000 */
+ priv->bar1_pci_adr &= priv->bar1_size - 1; /* Fix alignment of BAR1 */
+ grpci_cfg_w32(host, PCI_BASE_ADDRESS_1, priv->bar1_pci_adr);
+ priv->regs->page1 = priv->bar1_pci_adr;
+
+ /* Translate I/O accesses 1:1 */
+ priv->regs->iomap = priv->pci_io & 0xffff0000;
+
+ /* set as bus master and enable pci memory responses */
+ grpci_cfg_r32(host, PCI_COMMAND, &data);
+ data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ grpci_cfg_w32(host, PCI_COMMAND, data);
+
+ /* unmask all PCI interrupts at PCI Core, not all GRPCI cores support
+ * this
+ */
+ priv->regs->irq = 0xf0000;
+
+ /* Successful */
+ return 0;
+}
+
+/* Initializes the GRPCI core and driver, must be called before calling init_pci()
+ *
+ * Return values
+ * 0 Successful initalization
+ * -1 Error during initialization, for example "PCI core not found".
+ * -2 Error PCI controller not HOST (targets not supported)
+ * -3 Error due to GRPCI hardware initialization
+ * -4 Error registering driver to PCI layer
+ */
+int grpci_init(struct grpci_priv *priv)
+{
+ struct ambapp_apb_info *apb;
+ struct ambapp_ahb_info *ahb;
+ int pin;
+ union drvmgr_key_value *value;
+ char keyname[6];
+ struct amba_dev_info *ainfo = priv->dev->businfo;
+
+ /* Find PCI core from Plug&Play information */
+ apb = ainfo->info.apb_slv;
+ ahb = ainfo->info.ahb_slv;
+
+ /* Found PCI core, init private structure */
+ priv->irq = apb->irq;
+ priv->regs = (struct grpci_regs *)apb->start;
+ priv->bt_enabled = DEFAULT_BT_ENABLED;
+
+ /* Calculate the PCI windows
+ * AMBA->PCI Window: AHB SLAVE AREA0
+ * AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
+ * AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
+ */
+ priv->pci_area = ahb->start[0];
+ priv->pci_area_end = ahb->start[0] + ahb->mask[0];
+ priv->pci_io = ahb->start[1];
+ priv->pci_conf = ahb->start[1] + (ahb->mask[1] >> 1);
+ priv->pci_conf_end = ahb->start[1] + ahb->mask[1];
+
+ /* On systems where PCI I/O area and configuration area is apart of the "PCI Window"
+ * the PCI Window stops at the start of the PCI I/O area
+ */
+ if ( (priv->pci_io > priv->pci_area) && (priv->pci_io < (priv->pci_area_end-1)) ) {
+ priv->pci_area_end = priv->pci_io;
+ }
+
+ /* Init PCI interrupt assignment table to all use the interrupt routed through
+ * the GRPCI core.
+ */
+ strcpy(keyname, "INTX#");
+ for (pin=1; pin<5; pin++) {
+ if ( grpci_pci_irq_table[pin-1] == 0xff ) {
+ grpci_pci_irq_table[pin-1] = priv->irq;
+
+ /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
+ keyname[3] = 'A' + (pin-1);
+ value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT);
+ if ( value )
+ grpci_pci_irq_table[pin-1] = value->i;
+ }
+ }
+
+ /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
+ value = drvmgr_dev_key_get(priv->dev, "byteTwisting", KEY_TYPE_INT);
+ if ( value )
+ priv->bt_enabled = value->i;
+
+ /* Use GRPCI target BAR1 to map CPU RAM to PCI, this is to make it
+ * possible for PCI peripherals to do DMA directly to CPU memory.
+ */
+ value = drvmgr_dev_key_get(priv->dev, "tgtbar1", KEY_TYPE_INT);
+ if (value)
+ priv->bar1_pci_adr = value->i;
+ else
+ priv->bar1_pci_adr = SYSTEM_MAINMEM_START; /* default */
+
+ /* This driver only support HOST systems, we check for HOST */
+ if ( !(priv->regs->cfg_stat & CFGSTAT_HOST) ) {
+ /* Target not supported */
+ return -2;
+ }
+
+ /* Init the PCI Core */
+ if ( grpci_hw_init(priv) ) {
+ return -3;
+ }
+
+ /* Down streams translation table */
+ priv->maps_down[0].name = "AMBA -> PCI MEM Window";
+ priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
+ priv->maps_down[0].from_adr = (void *)priv->pci_area;
+ priv->maps_down[0].to_adr = (void *)priv->pci_area;
+ /* End table */
+ priv->maps_down[1].size = 0;
+
+ /* Up streams translation table */
+ priv->maps_up[0].name = "Target BAR1 -> AMBA";
+ priv->maps_up[0].size = priv->bar1_size;
+ priv->maps_up[0].from_adr = (void *)priv->bar1_pci_adr;
+ priv->maps_up[0].to_adr = (void *)priv->bar1_pci_adr;
+ /* End table */
+ priv->maps_up[1].size = 0;
+
+ return 0;
+}
+
+/* Called when a core is found with the AMBA device and vendor ID
+ * given in grpci_ids[]. IRQ, Console does not work here
+ */
+int grpci_init1(struct drvmgr_dev *dev)
+{
+ int status;
+ struct grpci_priv *priv;
+ struct pci_auto_setup grpci_auto_cfg;
+
+ DBG("GRPCI[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
+
+ if ( grpci_minor != 0 ) {
+ DBG("Driver only supports one PCI core\n");
+ return DRVMGR_FAIL;
+ }
+
+ if ( (strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
+ (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0) ) {
+ /* We only support GRPCI driver on local bus */
+ return DRVMGR_FAIL;
+ }
+
+ priv = dev->priv;
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ priv->dev = dev;
+ priv->minor = grpci_minor++;
+
+ grpcipriv = priv;
+ status = grpci_init(priv);
+ if (status) {
+ printf("Failed to initialize grpci driver %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+
+ /* Register the PCI core at the PCI layers */
+
+ if (priv->bt_enabled == 0) {
+ /* Host is Big-Endian */
+ pci_endian = PCI_BIG_ENDIAN;
+
+ memcpy(&grpci_access_drv.io, &grpci_io_ops_be,
+ sizeof(grpci_io_ops_be));
+ grpci_access_drv.memreg = &pci_memreg_sparc_be_ops;
+ }
+
+ if (pci_access_drv_register(&grpci_access_drv)) {
+ /* Access routines registration failed */
+ return DRVMGR_FAIL;
+ }
+
+ /* Prepare memory MAP */
+ grpci_auto_cfg.options = 0;
+ grpci_auto_cfg.mem_start = 0;
+ grpci_auto_cfg.mem_size = 0;
+ grpci_auto_cfg.memio_start = priv->pci_area;
+ grpci_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
+ grpci_auto_cfg.io_start = priv->pci_io;
+ grpci_auto_cfg.io_size = priv->pci_conf - priv->pci_io;
+ grpci_auto_cfg.irq_map = grpci_bus0_irq_map;
+ grpci_auto_cfg.irq_route = NULL; /* use standard routing */
+ pci_config_register(&grpci_auto_cfg);
+
+ if (pci_config_init()) {
+ /* PCI configuration failed */
+ return DRVMGR_FAIL;
+ }
+
+ priv->config.maps_down = &priv->maps_down[0];
+ priv->config.maps_up = &priv->maps_up[0];
+ return pcibus_register(dev, &priv->config);
+}
+
+/* DMA functions which uses GRPCIs optional DMA controller (len in words) */
+int grpci_dma_to_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) {
+ int ret = 0;
+
+ pcidma[0] = 0x82;
+ pcidma[1] = ahb_addr;
+ pcidma[2] = pci_addr;
+ pcidma[3] = len;
+ pcidma[0] = 0x83;
+
+ while ( (pcidma[0] & 0x4) == 0)
+ ;
+
+ if (pcidma[0] & 0x8) { /* error */
+ ret = -1;
+ }
+
+ pcidma[0] |= 0xC;
+ return ret;
+
+}
+
+int grpci_dma_from_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) {
+ int ret = 0;
+
+ pcidma[0] = 0x80;
+ pcidma[1] = ahb_addr;
+ pcidma[2] = pci_addr;
+ pcidma[3] = len;
+ pcidma[0] = 0x81;
+
+ while ( (pcidma[0] & 0x4) == 0)
+ ;
+
+ if (pcidma[0] & 0x8) { /* error */
+ ret = -1;
+ }
+
+ pcidma[0] |= 0xC;
+ return ret;
+
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/grpci2.c b/c/src/lib/libbsp/sparc/shared/pci/grpci2.c
new file mode 100644
index 0000000..55a69ef
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/grpci2.c
@@ -0,0 +1,902 @@
+/* GRLIB GRPCI2 PCI HOST driver.
+ *
+ * COPYRIGHT (c) 2011
+ * Cobham Gaisler AB.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+/* Configures the GRPCI2 core and initialize,
+ * - the PCI Library (pci.c)
+ * - the general part of the PCI Bus driver (pci_bus.c)
+ *
+ * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
+ * default taken from Plug and Play, but may be overridden by the
+ * driver resources INTA#..INTD#. GRPCI2 handles differently depending
+ * on the design (4 different ways).
+ *
+ * GRPCI2 IRQ implementation notes
+ * -------------------------------
+ * Since the Driver Manager pci_bus layer implements IRQ by calling
+ * pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
+ * root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
+ * driver to use the drvmgr_interrupt_* routines since they will be
+ * accessing the same routines in the end. Otherwise the GRPCI2 driver must
+ * have used the pci_interrupt_* routines.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <rtems/bspIo.h>
+#include <libcpu/byteorder.h>
+#include <libcpu/access.h>
+#include <pci.h>
+#include <pci/cfg.h>
+
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <ambapp.h>
+#include <drvmgr/pci_bus.h>
+#include <grpci2.h>
+
+#ifndef IRQ_GLOBAL_PREPARE
+ #define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
+#endif
+
+#ifndef IRQ_GLOBAL_DISABLE
+ #define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
+#endif
+
+#ifndef IRQ_GLOBAL_ENABLE
+ #define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
+#endif
+
+/* If defined to 1 - byte twisting is enabled by default */
+#define DEFAULT_BT_ENABLED 0
+
+/* Interrupt assignment. Set to other value than 0xff in order to
+ * override defaults and plug&play information
+ */
+#ifndef GRPCI2_INTA_SYSIRQ
+ #define GRPCI2_INTA_SYSIRQ 0xff
+#endif
+#ifndef GRPCI2_INTB_SYSIRQ
+ #define GRPCI2_INTB_SYSIRQ 0xff
+#endif
+#ifndef GRPCI2_INTC_SYSIRQ
+ #define GRPCI2_INTC_SYSIRQ 0xff
+#endif
+#ifndef GRPCI2_INTD_SYSIRQ
+ #define GRPCI2_INTD_SYSIRQ 0xff
+#endif
+
+/*#define DEBUG 1*/
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define PCI_INVALID_VENDORDEVICEID 0xffffffff
+#define PCI_MULTI_FUNCTION 0x80
+
+/*
+ * GRPCI2 APB Register MAP
+ */
+struct grpci2_regs {
+ volatile unsigned int ctrl; /* 0x00 */
+ volatile unsigned int sts_cap; /* 0x04 */
+ int res1; /* 0x08 */
+ volatile unsigned int io_map; /* 0x0C */
+ volatile unsigned int dma_ctrl; /* 0x10 */
+ volatile unsigned int dma_bdbase; /* 0x14 */
+ int res2[2]; /* 0x18 */
+ volatile unsigned int bars[6]; /* 0x20 */
+ int res3[2]; /* 0x38 */
+ volatile unsigned int ahbmst_map[16]; /* 0x40 */
+};
+
+#define CTRL_BUS_BIT 16
+
+#define CTRL_SI (1<<27)
+#define CTRL_PE (1<<26)
+#define CTRL_EI (1<<25)
+#define CTRL_ER (1<<24)
+#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
+#define CTRL_HOSTINT 0xf
+
+#define STS_HOST_BIT 31
+#define STS_MST_BIT 30
+#define STS_TAR_BIT 29
+#define STS_DMA_BIT 28
+#define STS_DI_BIT 27
+#define STS_HI_BIT 26
+#define STS_IRQMODE_BIT 24
+#define STS_TRACE_BIT 23
+#define STS_CFGERRVALID_BIT 20
+#define STS_CFGERR_BIT 19
+#define STS_INTTYPE_BIT 12
+#define STS_INTSTS_BIT 8
+#define STS_FDEPTH_BIT 2
+#define STS_FNUM_BIT 0
+
+#define STS_HOST (1<<STS_HOST_BIT)
+#define STS_MST (1<<STS_MST_BIT)
+#define STS_TAR (1<<STS_TAR_BIT)
+#define STS_DMA (1<<STS_DMA_BIT)
+#define STS_DI (1<<STS_DI_BIT)
+#define STS_HI (1<<STS_HI_BIT)
+#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
+#define STS_TRACE (1<<STS_TRACE_BIT)
+#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
+#define STS_CFGERR (1<<STS_CFGERR_BIT)
+#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
+#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
+#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
+#define STS_FNUM (0x3<<STS_FNUM_BIT)
+
+#define STS_ISYSERR (1<<17)
+#define STS_IDMA (1<<16)
+#define STS_IDMAERR (1<<15)
+#define STS_IMSTABRT (1<<14)
+#define STS_ITGTABRT (1<<13)
+#define STS_IPARERR (1<<12)
+
+struct grpci2_bd_chan {
+ volatile unsigned int ctrl; /* 0x00 DMA Control */
+ volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
+ volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
+ volatile unsigned int res; /* 0x0C Reserved */
+};
+
+#define BD_CHAN_EN 0x80000000
+#define BD_CHAN_TYPE 0x00300000
+#define BD_CHAN_BDCNT 0x0000ffff
+#define BD_CHAN_EN_BIT 31
+#define BD_CHAN_TYPE_BIT 20
+#define BD_CHAN_BDCNT_BIT 0
+
+struct grpci2_bd_data {
+ volatile unsigned int ctrl; /* 0x00 DMA Data Control */
+ volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
+ volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
+ volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
+};
+
+#define BD_DATA_EN 0x80000000
+#define BD_DATA_IE 0x40000000
+#define BD_DATA_DR 0x20000000
+#define BD_DATA_TYPE 0x00300000
+#define BD_DATA_ER 0x00080000
+#define BD_DATA_LEN 0x0000ffff
+#define BD_DATA_EN_BIT 31
+#define BD_DATA_IE_BIT 30
+#define BD_DATA_DR_BIT 29
+#define BD_DATA_TYPE_BIT 20
+#define BD_DATA_ER_BIT 19
+#define BD_DATA_LEN_BIT 0
+
+/* GRPCI2 Capability */
+struct grpci2_cap_first {
+ unsigned int ctrl;
+ unsigned int pci2ahb_map[6];
+ unsigned int ext2ahb_map;
+ unsigned int io_map;
+ unsigned int pcibar_size[6];
+};
+#define CAP9_CTRL_OFS 0
+#define CAP9_BAR_OFS 0x4
+#define CAP9_IOMAP_OFS 0x20
+#define CAP9_BARSIZE_OFS 0x24
+
+struct grpci2_priv *grpci2priv = NULL;
+
+/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
+ * to a system interrupt number.
+ */
+unsigned char grpci2_pci_irq_table[4] =
+{
+ /* INTA# */ GRPCI2_INTA_SYSIRQ,
+ /* INTB# */ GRPCI2_INTB_SYSIRQ,
+ /* INTC# */ GRPCI2_INTC_SYSIRQ,
+ /* INTD# */ GRPCI2_INTD_SYSIRQ
+};
+
+/* Start of workspace/dynamical area */
+extern unsigned int _end;
+#define DMA_START ((unsigned int) &_end)
+
+/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
+struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
+ /* BAR0 */ {DMA_START, DMA_START, 0x10000000},
+ /* BAR1 */ {0, 0, 0},
+ /* BAR2 */ {0, 0, 0},
+ /* BAR3 */ {0, 0, 0},
+ /* BAR4 */ {0, 0, 0},
+ /* BAR5 */ {0, 0, 0},
+};
+
+/* Driver private data struture */
+struct grpci2_priv {
+ struct drvmgr_dev *dev;
+ struct grpci2_regs *regs;
+ char irq;
+ char irq_mode; /* IRQ Mode from CAPSTS REG */
+ char bt_enabled;
+ unsigned int irq_mask;
+
+ struct grpci2_pcibar_cfg *barcfg;
+
+ unsigned int pci_area;
+ unsigned int pci_area_end;
+ unsigned int pci_io;
+ unsigned int pci_conf;
+ unsigned int pci_conf_end;
+
+ uint32_t devVend; /* Host PCI Device/Vendor ID */
+
+ struct drvmgr_map_entry maps_up[7];
+ struct drvmgr_map_entry maps_down[2];
+ struct pcibus_config config;
+};
+
+int grpci2_init1(struct drvmgr_dev *dev);
+int grpci2_init3(struct drvmgr_dev *dev);
+
+/* GRPCI2 DRIVER */
+
+struct drvmgr_drv_ops grpci2_ops =
+{
+ .init = {grpci2_init1, NULL, grpci2_init3, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct amba_dev_id grpci2_ids[] =
+{
+ {VENDOR_GAISLER, GAISLER_GRPCI2},
+ {0, 0} /* Mark end of table */
+};
+
+struct amba_drv_info grpci2_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
+ "GRPCI2_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
+ &grpci2_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
+ },
+ &grpci2_ids[0]
+};
+
+void grpci2_register_drv(void)
+{
+ DBG("Registering GRPCI2 driver\n");
+ drvmgr_drv_register(&grpci2_info.general);
+}
+
+int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
+{
+ struct grpci2_priv *priv = grpci2priv;
+ volatile uint32_t *pci_conf;
+ unsigned int tmp, devfn;
+ IRQ_GLOBAL_PREPARE(oldLevel);
+ int retval, bus = PCI_DEV_BUS(dev);
+
+ if ((unsigned int)ofs & 0xffffff03) {
+ retval = PCISTS_EINVAL;
+ goto out2;
+ }
+
+ if (PCI_DEV_SLOT(dev) > 15) {
+ retval = PCISTS_MSTABRT;
+ goto out;
+ }
+
+ /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
+ * we skip them.
+ */
+ if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
+ devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
+ else
+ devfn = PCI_DEV_DEVFUNC(dev);
+
+ pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
+
+ IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
+
+ /* Select bus */
+ priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
+ /* clear old status */
+ priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
+
+ tmp = *pci_conf;
+
+ /* Wait until GRPCI2 signals that CFG access is done, it should be
+ * done instantaneously unless a DMA operation is ongoing...
+ */
+ while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
+ ;
+
+ if (priv->regs->sts_cap & STS_CFGERR) {
+ retval = PCISTS_MSTABRT;
+ } else {
+ /* Bus always little endian (unaffected by byte-swapping) */
+ *val = CPU_swap_u32(tmp);
+ retval = PCISTS_OK;
+ }
+
+ IRQ_GLOBAL_ENABLE(oldLevel);
+
+out:
+ if (retval != PCISTS_OK)
+ *val = 0xffffffff;
+
+ DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
+
+out2:
+ return retval;
+}
+
+int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
+ *val = 0xffff & (v >> (8*(ofs & 0x3)));
+
+ return retval;
+}
+
+int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
+
+ *val = 0xff & (v >> (8*(ofs & 3)));
+
+ return retval;
+}
+
+int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
+{
+ struct grpci2_priv *priv = grpci2priv;
+ volatile uint32_t *pci_conf;
+ uint32_t value, devfn;
+ int retval, bus = PCI_DEV_BUS(dev);
+ IRQ_GLOBAL_PREPARE(oldLevel);
+
+ if ((unsigned int)ofs & 0xffffff03)
+ return PCISTS_EINVAL;
+
+ if (PCI_DEV_SLOT(dev) > 15)
+ return PCISTS_MSTABRT;
+
+ value = CPU_swap_u32(val);
+
+ /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
+ * we skip them.
+ */
+ if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
+ devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
+ else
+ devfn = PCI_DEV_DEVFUNC(dev);
+
+ pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
+
+ IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
+
+ /* Select bus */
+ priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
+ /* clear old status */
+ priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
+
+ *pci_conf = value;
+
+ /* Wait until GRPCI2 signals that CFG access is done, it should be
+ * done instantaneously unless a DMA operation is ongoing...
+ */
+ while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
+ ;
+
+ if (priv->regs->sts_cap & STS_CFGERR)
+ retval = PCISTS_MSTABRT;
+ else
+ retval = PCISTS_OK;
+
+ IRQ_GLOBAL_ENABLE(oldLevel);
+
+ DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
+
+ return retval;
+}
+
+int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
+
+ return grpci2_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
+
+ return grpci2_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+/* Return the assigned system IRQ number that corresponds to the PCI
+ * "Interrupt Pin" information from configuration space.
+ *
+ * The IRQ information is stored in the grpci2_pci_irq_table configurable
+ * by the user.
+ *
+ * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
+ * 0xff if not assigned.
+ */
+uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
+{
+ uint8_t sysIrqNr = 0; /* not assigned */
+ int irq_group;
+
+ if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
+ /* Use default IRQ decoding on PCI BUS0 according slot numbering */
+ irq_group = PCI_DEV_SLOT(dev) & 0x3;
+ irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
+ /* Valid PCI "Interrupt Pin" number */
+ sysIrqNr = grpci2_pci_irq_table[irq_pin];
+ }
+ return sysIrqNr;
+}
+
+int grpci2_translate(uint32_t *address, int type, int dir)
+{
+ uint32_t adr, start, end;
+ struct grpci2_priv *priv = grpci2priv;
+ int i;
+
+ if (type == 1) {
+ /* I/O */
+ if (dir != 0) {
+ /* The PCI bus can not access the CPU bus from I/O
+ * because GRPCI2 core does not support I/O BARs
+ */
+ return -1;
+ }
+
+ /* We have got a PCI IO BAR address that the CPU want to access.
+ * Check that it is within the PCI I/O window, I/O adresses
+ * are NOT mapped 1:1 with GRPCI2 driver... translation needed.
+ */
+ adr = *(uint32_t *)address;
+ if (adr < 0x100 || adr > 0x10000)
+ return -1;
+ *address = adr + priv->pci_io;
+ } else {
+ /* MEMIO and MEM.
+ * Memory space is mapped 1:1 so no translation is needed.
+ * Check that address is within accessible windows.
+ */
+ adr = *(uint32_t *)address;
+ if (dir == 0) {
+ /* PCI BAR to AMBA-CPU address.. check that it is
+ * located within GRPCI2 PCI Memory Window
+ * adr = PCI address.
+ */
+ if (adr < priv->pci_area || adr >= priv->pci_area_end)
+ return -1;
+ } else {
+ /* We have a CPU address and want to get access to it
+ * from PCI space, typically when doing DMA into CPU
+ * RAM. The GRPCI2 core may have multiple target BARs
+ * that PCI masters can access, the BARs are user
+ * configurable in the following ways:
+ * BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
+ *
+ * The below code tries to find a BAR for which the
+ * AMBA bar may have been mapped onto, and translate
+ * the AMBA-CPU address into a PCI address using the
+ * given mapping.
+ *
+ * adr = AMBA address.
+ */
+ for(i=0; i<6; i++) {
+ start = priv->barcfg[i].ahbadr;
+ end = priv->barcfg[i].ahbadr +
+ priv->barcfg[i].barsize;
+ if (adr >= start && adr < end) {
+ /* BAR match: Translate address */
+ *address = (adr - start) +
+ priv->barcfg[i].pciadr;
+ return 0;
+ }
+ }
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
+extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
+
+/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
+struct pci_access_drv grpci2_access_drv = {
+ .cfg =
+ {
+ grpci2_cfg_r8,
+ grpci2_cfg_r16,
+ grpci2_cfg_r32,
+ grpci2_cfg_w8,
+ grpci2_cfg_w16,
+ grpci2_cfg_w32,
+ },
+ .io =
+ {
+ _ld8,
+ _ld_le16,
+ _ld_le32,
+ _st8,
+ _st_le16,
+ _st_le32,
+ },
+ .memreg = &pci_memreg_sparc_le_ops,
+ .translate = grpci2_translate,
+};
+
+struct pci_io_ops grpci2_io_ops_be =
+{
+ _ld8,
+ _ld_be16,
+ _ld_be32,
+ _st8,
+ _st_be16,
+ _st_be32,
+};
+
+/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
+ * Abort.
+ */
+void grpci2_err_isr(void *arg)
+{
+ struct grpci2_priv *priv = arg;
+ unsigned int sts = priv->regs->sts_cap;
+
+ if (sts & (STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR | STS_ISYSERR)) {
+ /* A PCI error IRQ ... Error handler unimplemented
+ * add your code here...
+ */
+ if (sts & STS_IMSTABRT) {
+ printk("GRPCI2: unhandled Master Abort IRQ\n");
+ }
+ if (sts & STS_ITGTABRT) {
+ printk("GRPCI2: unhandled Target Abort IRQ\n");
+ }
+ if (sts & STS_IPARERR) {
+ printk("GRPCI2: unhandled Parity Error IRQ\n");
+ }
+ if (sts & STS_ISYSERR) {
+ printk("GRPCI2: unhandled System Error IRQ\n");
+ }
+ }
+}
+
+int grpci2_hw_init(struct grpci2_priv *priv)
+{
+ struct grpci2_regs *regs = priv->regs;
+ int i;
+ uint8_t capptr;
+ uint32_t data, io_map, ahbadr, pciadr, size;
+ pci_dev_t host = PCI_DEV(0, 0, 0);
+ struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
+
+ /* Reset any earlier setup */
+ regs->ctrl = 0;
+ regs->sts_cap = ~0; /* Clear Status */
+ regs->dma_ctrl = 0;
+ regs->dma_bdbase = 0;
+
+ /* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
+ regs->io_map = priv->pci_io & 0xffff0000;
+
+ /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
+ * Each AHB master has it's own mapping registers. Max 16 AHB masters.
+ */
+ for (i=0; i<16; i++)
+ regs->ahbmst_map[i] = priv->pci_area;
+
+ /* Get the GRPCI2 Host PCI ID */
+ grpci2_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+
+ /* Get address to first (always defined) capability structure */
+ grpci2_cfg_r8(host, PCI_CAP_PTR, &capptr);
+ if (capptr == 0)
+ return -1;
+
+ /* Enable/Disable Byte twisting */
+ grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
+ io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
+ grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
+
+ /* Setup the Host's PCI Target BARs for others to access (DMA) */
+ for (i=0; i<6; i++) {
+ /* Make sure address is properly aligned */
+ size = ~(barcfg[i].barsize-1);
+ barcfg[i].pciadr &= size;
+ barcfg[i].ahbadr &= size;
+
+ pciadr = barcfg[i].pciadr;
+ ahbadr = barcfg[i].ahbadr;
+ size |= PCI_BASE_ADDRESS_MEM_PREFETCH;
+
+ grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
+ grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
+ grpci2_cfg_w32(host, PCI_BASE_ADDRESS_0+i*4, pciadr);
+ }
+
+ /* set as bus master and enable pci memory responses */
+ grpci2_cfg_r32(host, PCI_COMMAND, &data);
+ data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ grpci2_cfg_w32(host, PCI_COMMAND, data);
+
+ /* Enable Error respone (CPU-TRAP) on illegal memory access */
+ regs->ctrl = CTRL_ER | CTRL_PE;
+
+ /* Successful */
+ return 0;
+}
+
+/* Initializes the GRPCI2 core and driver, must be called before calling
+ * init_pci()
+ *
+ * Return values
+ * 0 Successful initalization
+ * -1 Error during initialization, for example "PCI core not found".
+ * -2 Error PCI controller not HOST (targets not supported)
+ * -3 Error due to GRPCI2 hardware initialization
+ */
+int grpci2_init(struct grpci2_priv *priv)
+{
+ struct ambapp_apb_info *apb;
+ struct ambapp_ahb_info *ahb;
+ int pin, i, j;
+ union drvmgr_key_value *value;
+ char keyname[6];
+ struct amba_dev_info *ainfo = priv->dev->businfo;
+ struct grpci2_pcibar_cfg *barcfg;
+ unsigned int size;
+
+ /* Find PCI core from Plug&Play information */
+ apb = ainfo->info.apb_slv;
+ ahb = ainfo->info.ahb_slv;
+
+ /* Found PCI core, init private structure */
+ priv->irq = apb->irq;
+ priv->regs = (struct grpci2_regs *)apb->start;
+ priv->bt_enabled = DEFAULT_BT_ENABLED;
+ priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
+
+ /* Calculate the PCI windows
+ * AMBA->PCI Window: AHB SLAVE AREA0
+ * AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
+ * AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
+ */
+ priv->pci_area = ahb->start[0];
+ priv->pci_area_end = ahb->start[0] + ahb->mask[0];
+ priv->pci_io = ahb->start[1];
+ priv->pci_conf = ahb->start[1] + 0x10000;
+ priv->pci_conf_end = priv->pci_conf + 0x10000;
+
+ /* On systems where PCI I/O area and configuration area is apart of the
+ * "PCI Window" the PCI Window stops at the start of the PCI I/O area
+ */
+ if ((priv->pci_io > priv->pci_area) &&
+ (priv->pci_io < (priv->pci_area_end-1))) {
+ priv->pci_area_end = priv->pci_io;
+ }
+
+ /* Init PCI interrupt assignment table to all use the interrupt routed
+ * through the GRPCI2 core.
+ */
+ strcpy(keyname, "INTX#");
+ for (pin=1; pin<5; pin++) {
+ if (grpci2_pci_irq_table[pin-1] == 0xff) {
+ if (priv->irq_mode < 2) {
+ /* PCI Interrupts are shared */
+ grpci2_pci_irq_table[pin-1] = priv->irq;
+ } else {
+ /* Unique IRQ per PCI INT Pin */
+ grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
+ }
+
+ /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
+ keyname[3] = 'A' + (pin-1);
+ value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT);
+ if (value)
+ grpci2_pci_irq_table[pin-1] = value->i;
+ }
+
+ /* Remember which IRQs are enabled */
+ if (grpci2_pci_irq_table[pin-1] != 0)
+ priv->irq_mask |= 1 << (pin-1);
+ }
+
+ /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
+ value = drvmgr_dev_key_get(priv->dev, "byteTwisting", KEY_TYPE_INT);
+ if (value)
+ priv->bt_enabled = value->i;
+
+ /* Let user Configure the 6 target BARs */
+ value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", KEY_TYPE_POINTER);
+ if (value)
+ priv->barcfg = value->ptr;
+ else
+ priv->barcfg = grpci2_default_bar_mapping;
+
+ /* This driver only support HOST systems, we check that it can act as a
+ * PCI Master and that it is in the Host slot. */
+ if ((priv->regs->sts_cap&STS_HOST) || !(priv->regs->sts_cap&STS_MST))
+ return -2; /* Target not supported */
+
+ /* Init the PCI Core */
+ if (grpci2_hw_init(priv))
+ return -3;
+
+ /* Down streams translation table */
+ priv->maps_down[0].name = "AMBA -> PCI MEM Window";
+ priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
+ priv->maps_down[0].from_adr = (void *)priv->pci_area;
+ priv->maps_down[0].to_adr = (void *)priv->pci_area;
+ /* End table */
+ priv->maps_down[1].size = 0;
+
+ /* Up streams translation table */
+ /* Setup the Host's PCI Target BARs for others to access (DMA) */
+ barcfg = priv->barcfg;
+ for (i=0,j=0; i<6; i++) {
+ size = barcfg[i].barsize;
+ if (size == 0)
+ continue;
+
+ /* Make sure address is properly aligned */
+ priv->maps_up[j].name = "Target BAR[I] -> AMBA";
+ priv->maps_up[j].size = size;
+ priv->maps_up[j].from_adr = (void *)
+ (barcfg[i].pciadr & ~(size - 1));
+ priv->maps_up[j].to_adr = (void *)
+ (barcfg[i].ahbadr & ~(size - 1));
+ j++;
+ }
+
+ /* End table */
+ priv->maps_up[j].size = 0;
+
+ return 0;
+}
+
+/* Called when a core is found with the AMBA device and vendor ID
+ * given in grpci2_ids[]. IRQ, Console does not work here
+ */
+int grpci2_init1(struct drvmgr_dev *dev)
+{
+ int status;
+ struct grpci2_priv *priv;
+ struct pci_auto_setup grpci2_auto_cfg;
+
+ DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
+
+ if (grpci2priv) {
+ DBG("Driver only supports one PCI core\n");
+ return DRVMGR_FAIL;
+ }
+
+ if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
+ (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
+ /* We only support GRPCI2 driver on local bus */
+ return DRVMGR_FAIL;
+ }
+
+ priv = dev->priv;
+ if (!priv)
+ return DRVMGR_NOMEM;
+
+ priv->dev = dev;
+ grpci2priv = priv;
+
+ /* Initialize GRPCI2 Hardware */
+ status = grpci2_init(priv);
+ if (status) {
+ printf("Failed to initialize grpci2 driver %d\n", status);
+ return -1;
+ }
+
+ /* Register the PCI core at the PCI layers */
+
+ if (priv->bt_enabled == 0) {
+ /* Host is Big-Endian */
+ pci_endian = PCI_BIG_ENDIAN;
+
+ memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
+ sizeof(grpci2_io_ops_be));
+ grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
+ }
+
+ if (pci_access_drv_register(&grpci2_access_drv)) {
+ /* Access routines registration failed */
+ return DRVMGR_FAIL;
+ }
+
+ /* Prepare memory MAP */
+ grpci2_auto_cfg.options = 0;
+ grpci2_auto_cfg.mem_start = 0;
+ grpci2_auto_cfg.mem_size = 0;
+ grpci2_auto_cfg.memio_start = priv->pci_area;
+ grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
+ grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
+ grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
+ grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
+ grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
+ pci_config_register(&grpci2_auto_cfg);
+
+ if (pci_config_init()) {
+ /* PCI configuration failed */
+ return DRVMGR_FAIL;
+ }
+
+ /* Initialize/Register Driver Manager PCI Bus */
+ priv->config.maps_down = &priv->maps_down[0];
+ priv->config.maps_up = &priv->maps_up[0];
+ return pcibus_register(dev, &priv->config);
+}
+
+int grpci2_init3(struct drvmgr_dev *dev)
+{
+ struct grpci2_priv *priv = dev->priv;
+
+ /* Install and Enable PCI Error interrupt handler */
+ drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
+
+ /* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
+ * safe every PCI board have to be resetted (no IRQ generation) before
+ * Global IRQs are enabled (Init is reached or similar)
+ */
+ priv->regs->ctrl |= (CTRL_EI | priv->irq_mask);
+
+ return DRVMGR_OK;
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_be.c b/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_be.c
new file mode 100644
index 0000000..fce96a9
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_be.c
@@ -0,0 +1,27 @@
+/* Registers-over-Memory Space - SPARC Big endian PCI bus definitions
+ *
+ * COPYRIGHT (c) 2011.
+ * Cobham Gaisler AB.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <pci.h>
+#include <libcpu/access.h>
+
+struct pci_memreg_ops pci_memreg_sparc_be_ops = {
+ .ld8 = _ld8,
+ .st8 = _st8,
+
+ .ld_le16 = _ld_be16,
+ .st_le16 = _st_be16,
+ .ld_be16 = _ld_le16,
+ .st_be16 = _st_le16,
+
+ .ld_le32 = _ld_be32,
+ .st_le32 = _st_be32,
+ .ld_be32 = _ld_le32,
+ .st_be32 = _st_le32,
+};
diff --git a/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_le.c b/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_le.c
new file mode 100644
index 0000000..acf4c52
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/pci_memreg_sparc_le.c
@@ -0,0 +1,28 @@
+/* Registers-over-Memory Space - SPARC Little endian PCI bus definitions
+ *
+ * COPYRIGHT (c) 2011.
+ * Cobham Gaisler AB.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+
+#include <pci.h>
+#include <libcpu/access.h>
+
+struct pci_memreg_ops pci_memreg_sparc_le_ops = {
+ .ld8 = _ld8,
+ .st8 = _st8,
+
+ .ld_le16 = _ld_le16,
+ .st_le16 = _st_le16,
+ .ld_be16 = _ld_be16,
+ .st_be16 = _st_be16,
+
+ .ld_le32 = _ld_le32,
+ .st_le32 = _st_le32,
+ .ld_be32 = _ld_be32,
+ .st_be32 = _st_be32,
+};
diff --git a/c/src/lib/libbsp/sparc/shared/pci/pcif.c b/c/src/lib/libbsp/sparc/shared/pci/pcif.c
new file mode 100644
index 0000000..c69282d
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/pcif.c
@@ -0,0 +1,563 @@
+/* GRLIB PCIF PCI HOST driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the PCIF core and initialize,
+ * - the PCI Library (pci.c)
+ * - the general part of the PCI Bus driver (pci_bus.c)
+ *
+ * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
+ * default taken from Plug and Play, but may be overridden by the
+ * driver resources INTA#..INTD#.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <libcpu/byteorder.h>
+#include <libcpu/access.h>
+#include <pci.h>
+#include <pci/cfg.h>
+
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <ambapp.h>
+#include <drvmgr/pci_bus.h>
+
+#include <pci.h>
+#include <rtems/bspIo.h>
+#include <string.h>
+
+/* Configuration options */
+#define SYSTEM_MAINMEM_START 0x40000000
+
+/* Interrupt assignment. Set to other value than 0xff in order to
+ * override defaults and plug&play information
+ */
+#ifndef PCIF_INTA_SYSIRQ
+ #define PCIF_INTA_SYSIRQ 0xff
+#endif
+#ifndef PCIF_INTB_SYSIRQ
+ #define PCIF_INTB_SYSIRQ 0xff
+#endif
+#ifndef PCIF_INTC_SYSIRQ
+ #define PCIF_INTC_SYSIRQ 0xff
+#endif
+#ifndef PCIF_INTD_SYSIRQ
+ #define PCIF_INTD_SYSIRQ 0xff
+#endif
+
+/*#define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/*
+ * Bit encode for PCI_CONFIG_HEADER_TYPE register
+ */
+struct pcif_regs {
+ volatile unsigned int bars[4]; /* 0x00-0x10 */
+ volatile unsigned int bus; /* 0x10 */
+ volatile unsigned int map_io; /* 0x14 */
+ volatile unsigned int status; /* 0x18 */
+ volatile unsigned int intr; /* 0x1c */
+ int unused[(0x40-0x20)/4]; /* 0x20-0x40 */
+ volatile unsigned int maps[(0x80-0x40)/4]; /* 0x40-0x80*/
+};
+
+struct pcif_priv *pcifpriv = NULL;
+static int pcif_minor = 0;
+
+/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
+ * to a system interrupt number.
+ */
+unsigned char pcif_pci_irq_table[4] =
+{
+ /* INTA# */ PCIF_INTA_SYSIRQ,
+ /* INTB# */ PCIF_INTB_SYSIRQ,
+ /* INTC# */ PCIF_INTC_SYSIRQ,
+ /* INTD# */ PCIF_INTD_SYSIRQ
+};
+
+/* Driver private data struture */
+struct pcif_priv {
+ struct drvmgr_dev *dev;
+ struct pcif_regs *regs;
+ int irq;
+ int minor;
+ int irq_mask;
+
+ unsigned int pci_area;
+ unsigned int pci_area_end;
+ unsigned int pci_io;
+ unsigned int pci_conf;
+ unsigned int pci_conf_end;
+
+ uint32_t devVend; /* Host PCI Vendor/Device ID */
+ uint32_t bar1_size;
+
+ struct drvmgr_map_entry maps_up[2];
+ struct drvmgr_map_entry maps_down[2];
+ struct pcibus_config config;
+};
+
+int pcif_init1(struct drvmgr_dev *dev);
+int pcif_init3(struct drvmgr_dev *dev);
+
+/* PCIF DRIVER */
+
+struct drvmgr_drv_ops pcif_ops =
+{
+ .init = {pcif_init1, NULL, pcif_init3, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct amba_dev_id pcif_ids[] =
+{
+ {VENDOR_GAISLER, GAISLER_PCIF},
+ {0, 0} /* Mark end of table */
+};
+
+struct amba_drv_info pcif_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_AMBAPP_GAISLER_PCIF_ID, /* Driver ID */
+ "PCIF_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
+ &pcif_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct pcif_priv), /* Let drvmgr alloc private */
+ },
+ &pcif_ids[0]
+};
+
+void pcif_register_drv(void)
+{
+ DBG("Registering PCIF driver\n");
+ drvmgr_drv_register(&pcif_info.general);
+}
+
+int pcif_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
+{
+ struct pcif_priv *priv = pcifpriv;
+ volatile uint32_t *pci_conf;
+ unsigned int devfn = PCI_DEV_DEVFUNC(dev);
+ int retval;
+ int bus = PCI_DEV_BUS(dev);
+
+ if (ofs & 3)
+ return PCISTS_EINVAL;
+
+ if (PCI_DEV_SLOT(dev) > 21) {
+ *val = 0xffffffff;
+ return PCISTS_OK;
+ }
+
+ /* Select bus */
+ priv->regs->bus = bus << 16;
+
+ pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs);
+
+ *val = *pci_conf;
+
+ if (priv->regs->status & 0x30000000) {
+ *val = 0xffffffff;
+ retval = PCISTS_MSTABRT;
+ } else
+ retval = PCISTS_OK;
+
+ DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, *val);
+
+ return retval;
+}
+int pcif_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = pcif_cfg_r32(dev, ofs & ~0x3, &v);
+ *val = 0xffff & (v >> (8*(ofs & 0x3)));
+
+ return retval;
+}
+
+int pcif_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = pcif_cfg_r32(dev, ofs & ~0x3, &v);
+
+ *val = 0xff & (v >> (8*(ofs & 3)));
+
+ return retval;
+}
+
+int pcif_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
+{
+ struct pcif_priv *priv = pcifpriv;
+ volatile uint32_t *pci_conf;
+ uint32_t devfn = PCI_DEV_DEVFUNC(dev);
+ int bus = PCI_DEV_BUS(dev);
+
+ if (ofs & ~0xfc)
+ return PCISTS_EINVAL;
+
+ if (PCI_DEV_SLOT(dev) > 21)
+ return PCISTS_MSTABRT;
+
+ /* Select bus */
+ priv->regs->bus = bus << 16;
+
+ pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs);
+
+ *pci_conf = val;
+
+ DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n",
+ PCI_DEV_EXPAND(dev), ofs, pci_conf, value);
+
+ return PCISTS_OK;
+}
+
+int pcif_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
+{
+ uint32_t v;
+ int retval;
+
+ if (ofs & 1)
+ return PCISTS_EINVAL;
+
+ retval = pcif_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
+
+ return pcif_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+int pcif_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
+{
+ uint32_t v;
+ int retval;
+
+ retval = pcif_cfg_r32(dev, ofs & ~0x3, &v);
+ if (retval != PCISTS_OK)
+ return retval;
+
+ v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
+
+ return pcif_cfg_w32(dev, ofs & ~0x3, v);
+}
+
+
+/* Return the assigned system IRQ number that corresponds to the PCI
+ * "Interrupt Pin" information from configuration space.
+ *
+ * The IRQ information is stored in the pcif_pci_irq_table configurable
+ * by the user.
+ *
+ * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
+ * 0xff if not assigned.
+ */
+uint8_t pcif_bus0_irq_map(pci_dev_t dev, int irq_pin)
+{
+ uint8_t sysIrqNr = 0; /* not assigned */
+ int irq_group;
+
+ if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
+ /* Use default IRQ decoding on PCI BUS0 according slot numbering */
+ irq_group = PCI_DEV_SLOT(dev) & 0x3;
+ irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
+ /* Valid PCI "Interrupt Pin" number */
+ sysIrqNr = pcif_pci_irq_table[irq_pin];
+ }
+ return sysIrqNr;
+}
+
+int pcif_translate(uint32_t *address, int type, int dir)
+{
+ /* No address translation implmented at this point */
+ return 0;
+}
+
+extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
+
+/* PCIF Big-Endian PCI access routines */
+struct pci_access_drv pcif_access_drv = {
+ .cfg =
+ {
+ pcif_cfg_r8,
+ pcif_cfg_r16,
+ pcif_cfg_r32,
+ pcif_cfg_w8,
+ pcif_cfg_w16,
+ pcif_cfg_w32,
+ },
+ .io = /* PCIF only supports Big-endian */
+ {
+ _ld8,
+ _ld_be16,
+ _ld_be32,
+ _st8,
+ _st_be16,
+ _st_be32,
+ },
+ .memreg = &pci_memreg_sparc_be_ops,
+ .translate = pcif_translate,
+};
+
+/* Initializes the PCIF core hardware
+ *
+ */
+int pcif_hw_init(struct pcif_priv *priv)
+{
+ struct pcif_regs *regs;
+ uint32_t data, size;
+ int mst;
+ pci_dev_t host = PCI_DEV(0, 0, 0);
+
+ regs = priv->regs;
+
+ /* Mask PCI interrupts */
+ regs->intr = 0;
+
+ /* Get the PCIF Host PCI ID */
+ pcif_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
+
+ /* set 1:1 mapping between AHB -> PCI memory space, for all Master cores */
+ for ( mst=0; mst<16; mst++) {
+ regs->maps[mst] = priv->pci_area;
+
+ /* Check if this register is implemented */
+ if ( regs->maps[mst] != priv->pci_area )
+ break;
+ }
+
+ /* and map system RAM at pci address SYSTEM_MAINMEM_START. This way
+ * PCI targets can do DMA directly into CPU main memory.
+ */
+ regs->bars[0] = SYSTEM_MAINMEM_START;
+ regs->bars[1] = 0;
+ regs->bars[2] = 0;
+ regs->bars[3] = 0;
+
+ /* determine size of target BAR1 */
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, 0xffffffff);
+ pcif_cfg_r32(host, PCI_BASE_ADDRESS_1, &size);
+ priv->bar1_size = (~(size & ~0xf)) + 1;
+
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_0, 0);
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_1, SYSTEM_MAINMEM_START);
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_2, 0);
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_3, 0);
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_4, 0);
+ pcif_cfg_w32(host, PCI_BASE_ADDRESS_5, 0);
+
+ /* set as bus master and enable pci memory responses */
+ pcif_cfg_r32(host, PCI_COMMAND, &data);
+ data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pcif_cfg_w32(host, PCI_COMMAND, data);
+
+ /* Successful */
+ return 0;
+}
+
+/* Initializes the PCIF core and driver, must be called before calling init_pci()
+ *
+ * Return values
+ * 0 Successful initalization
+ * -1 Error during initialization, for example "PCI core not found".
+ * -2 Error PCI controller not HOST (targets not supported)
+ * -3 Error due to PCIF hardware initialization
+ * -4 Error registering driver to PCI layer
+ */
+int pcif_init(struct pcif_priv *priv)
+{
+ struct ambapp_apb_info *apb;
+ struct ambapp_ahb_info *ahb;
+ int pin;
+ union drvmgr_key_value *value;
+ char keyname[6];
+ struct amba_dev_info *ainfo = priv->dev->businfo;
+
+ /* Find PCI core from Plug&Play information */
+ apb = ainfo->info.apb_slv;
+ ahb = ainfo->info.ahb_slv;
+
+ /* Found PCI core, init private structure */
+ priv->irq = apb->irq;
+ priv->regs = (struct pcif_regs *)apb->start;
+
+ /* Calculate the PCI windows
+ * AMBA->PCI Window: AHB SLAVE AREA0
+ * AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
+ * AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
+ */
+ priv->pci_area = ahb->start[0];
+ priv->pci_area_end = ahb->start[0] + ahb->mask[0];
+ priv->pci_io = ahb->start[1];
+ priv->pci_conf = ahb->start[1] + (ahb->mask[1] >> 1);
+ priv->pci_conf_end = ahb->start[1] + ahb->mask[1];
+
+ /* On systems where PCI I/O area and configuration area is apart of the "PCI Window"
+ * the PCI Window stops at the start of the PCI I/O area
+ */
+ if ( (priv->pci_io > priv->pci_area) && (priv->pci_io < (priv->pci_area_end-1)) ) {
+ priv->pci_area_end = priv->pci_io;
+ }
+
+ /* Init PCI interrupt assignment table to all use the interrupt routed through
+ * the PCIF core.
+ */
+ strcpy(keyname, "INTX#");
+ for (pin=1; pin<5; pin++) {
+ if ( pcif_pci_irq_table[pin-1] == 0xff ) {
+ pcif_pci_irq_table[pin-1] = priv->irq;
+
+ /* User may override Plug & Play IRQ */
+ keyname[3] = 'A' + (pin-1);
+ value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT);
+ if ( value )
+ pcif_pci_irq_table[pin-1] = value->i;
+ }
+ }
+
+ priv->irq_mask = 0xf;
+ value = drvmgr_dev_key_get(priv->dev, "", KEY_TYPE_INT);
+ if ( value )
+ priv->irq_mask = value->i & 0xf;
+
+ /* This driver only support HOST systems, we check for HOST */
+ if ( priv->regs->status & 0x00000001 ) {
+ /* Target not supported */
+ return -2;
+ }
+
+ /* Init the PCI Core */
+ if ( pcif_hw_init(priv) ) {
+ return -3;
+ }
+
+ /* Down streams translation table */
+ priv->maps_down[0].name = "AMBA -> PCI MEM Window";
+ priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
+ priv->maps_down[0].from_adr = (void *)priv->pci_area;
+ priv->maps_down[0].to_adr = (void *)priv->pci_area;
+ /* End table */
+ priv->maps_down[1].size = 0;
+
+ /* Up streams translation table */
+ priv->maps_up[0].name = "Target BAR1 -> AMBA";
+ priv->maps_up[0].size = priv->bar1_size;
+ priv->maps_up[0].from_adr = (void *)SYSTEM_MAINMEM_START;
+ priv->maps_up[0].to_adr = (void *)SYSTEM_MAINMEM_START;
+ /* End table */
+ priv->maps_up[1].size = 0;
+
+ return 0;
+}
+
+/* Called when a core is found with the AMBA device and vendor ID
+ * given in pcif_ids[].
+ */
+int pcif_init1(struct drvmgr_dev *dev)
+{
+ struct pcif_priv *priv;
+ struct pci_auto_setup pcif_auto_cfg;
+
+ DBG("PCIF[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
+
+ if ( pcif_minor != 0 ) {
+ printf("Driver only supports one PCI core\n");
+ return DRVMGR_FAIL;
+ }
+
+ priv = dev->priv;
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ dev->priv = priv;
+ priv->dev = dev;
+ priv->minor = pcif_minor++;
+
+ pcifpriv = priv;
+ if ( pcif_init(priv) ) {
+ printf("Failed to initialize PCIF driver\n");
+ free(priv);
+ dev->priv = NULL;
+ return DRVMGR_FAIL;
+ }
+
+ /* Host is always Big-Endian */
+ pci_endian = PCI_BIG_ENDIAN;
+
+ /* Register the PCI core at the PCI layer */
+
+ if (pci_access_drv_register(&pcif_access_drv)) {
+ /* Access routines registration failed */
+ return DRVMGR_FAIL;
+ }
+
+ /* Prepare memory MAP */
+ pcif_auto_cfg.options = 0;
+ pcif_auto_cfg.mem_start = 0;
+ pcif_auto_cfg.mem_size = 0;
+ pcif_auto_cfg.memio_start = priv->pci_area;
+ pcif_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
+ pcif_auto_cfg.io_start = priv->pci_io;
+ pcif_auto_cfg.io_size = priv->pci_conf - priv->pci_io;
+ pcif_auto_cfg.irq_map = pcif_bus0_irq_map;
+ pcif_auto_cfg.irq_route = NULL; /* use standard routing */
+ pci_config_register(&pcif_auto_cfg);
+
+ if (pci_config_init()) {
+ /* PCI configuration failed */
+ return DRVMGR_FAIL;
+ }
+
+ priv->config.maps_down = &priv->maps_down[0];
+ priv->config.maps_up = &priv->maps_up[0];
+ return pcibus_register(dev, &priv->config);
+}
+
+int pcif_init3(struct drvmgr_dev *dev)
+{
+ struct pcif_priv *priv = dev->priv;
+
+ /* Unmask all interrupts, on some sytems this
+ * might be problematic because all PCI IRQs are
+ * not connected on the PCB or used for something
+ * else. The irqMask driver resource can be used to
+ * control which PCI IRQs are used to generate the
+ * PCI system IRQ, example:
+ *
+ * 0xf - enable all (DEFAULT)
+ * 0x8 - enable one PCI irq
+ *
+ * Before unmasking PCI IRQ, all PCI boards must
+ * have been initialized and IRQ turned off to avoid
+ * system hang.
+ */
+
+ priv->regs->intr = priv->irq_mask;
+
+ return DRVMGR_OK;
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/pcifinddevice.c b/c/src/lib/libbsp/sparc/shared/pci/pcifinddevice.c
deleted file mode 100644
index bd05aab..0000000
--- a/c/src/lib/libbsp/sparc/shared/pci/pcifinddevice.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Author: Till Straumann <strauman at slac.stanford.edu>, 2001 */
-
-/* find a particular PCI device
- * (we assume, the firmware configured the PCI bus[es] for us)
- */
-
-#include <pci.h>
-#include <rtems/bspIo.h>
-
-int
-BSP_pciFindDevice( unsigned short vendorid, unsigned short deviceid,
- int instance, int *pbus, int *pdev, int *pfun )
-{
- uint32_t d;
- unsigned short s;
- unsigned char bus,dev,fun,hd;
-
- for (bus=0; bus<BusCountPCI(); bus++) {
- for (dev=0; dev<PCI_MAX_DEVICES; dev++) {
-
- pci_read_config_byte(bus,dev,0, PCI_HEADER_TYPE, &hd);
- hd = (hd & PCI_HEADER_TYPE_MULTI_FUNCTION ? PCI_MAX_FUNCTIONS : 1);
-
- for (fun=0; fun<hd; fun++) {
- /*
- * The last devfn id/slot is special; must skip it
- */
- if (PCI_MAX_DEVICES-1==dev && PCI_MAX_FUNCTIONS-1 == fun)
- break;
- (void)pci_read_config_dword(bus,dev,fun,PCI_VENDOR_ID,&d);
- if (PCI_INVALID_VENDORDEVICEID == d)
- continue;
-#ifdef PCI_DEBUG
- printk("BSP_pciFindDevice: found 0x%08x at %d/%d/%d\n",d,bus,dev,fun);
-#endif
- (void) pci_read_config_word(bus,dev,fun,PCI_VENDOR_ID,&s);
- if (vendorid != s)
- continue;
- (void) pci_read_config_word(bus,dev,fun,PCI_DEVICE_ID,&s);
- if (deviceid == s) {
- if (instance--) continue;
- *pbus=bus; *pdev=dev; *pfun=fun;
- return 0;
- }
- }
- }
- }
- return -1;
-}
-
-/* eof */
--
1.7.0.4
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