[PATCH] bsp/xilinx-zynq: Correct the ZedBoard PERIPHCLK frequency

[Patrick Gauvin]

With the default CPU clock ratio of 6:2:1 with a PS_CLK of 33.33 MHz, the
CPU/SCU clock is 667 MHz (See UG585 v1.11 section 25.3). In the Zynq7000
series, PERIPHCLK is equivalent to the CPU/SCU clock divided by 2.

This was discovered by noticing that the ticker sample program was running
two times slower than expected.
---
 c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
index 99140c3..43dd43e 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
@@ -33,7 +33,7 @@ RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
 RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
 
 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U])
-RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U])
+RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[333333333U])
 RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
 RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
 
-- 
2.7.4