Interrupts strange behavior on RISC-V

[Joel Sherrill]

On Jul 8, 2017 10:09 AM, "Denis Obrezkov" <denisobrezkov at gmail.com> wrote:

Hello all,
I worked with local interrupts last few days and found some strange
behavior:


I am trying to handle local interrupts.
That's what I do, in my handler for timer interrupts:
* disable timer interrupts in mie
* read a current value from mtime
* copy it to mtimecmp (both are 64bit width types)
* add some big value to mtimecmp
* enable timer interrupts in mie.

And I have two boards and the problem is that on one of them interrupts are
permanently generated because mip register is always 1 in mtip position,
though mtimecmp is greater than mtime, and are not generated at all on the
other.

Is there a procedure for clearing the interrupt?

In this piece of code, I turn on interrupts:
la t0, RISCV_Exception_default
csrs mtvec, t0
li t0, 0x88
csrs mie, t0
csrsi mstatus, 0x8


Can you point us to the documentation and section where this timer behavior
is defined? Sometimes having someone else read it can provide a different
interpretation.

And is there other code like Linux which deals with this timer? There may
be a magic sequence you are missing

My start file:
https://github.com/embeddedden/rtems-riscv/blob/hifive1/c/src/lib/libbsp/
riscv32/hifive1/start/start.S

and ISR:
https://github.com/embeddedden/rtems-riscv/blob/hifive1/c/src/lib/libbsp/
riscv32/hifive1/irq/irq.c


I also posted this question here:

https://forums.sifive.com/t/how-to-deal-with-local-interrupts-in-hifive1/632

-- 
Regards, Denis Obrezkov
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