Zynq SMP CPU0 Not Waking CPU1

Misra, Avinash Avinash.Misra at jhuapl.edu
Mon Dec 17 21:49:29 UTC 2018


A little embarrassing but the problem has been solved. I was using SDK to load and run the image on my Zynq Board directly through SDK. Unbeknownst to me, SDK (even when using the RUN option instead of the DEBUG option) still hangs both processors and requires the user to start them up manually. By flashing the RTEMS image to Flash with the Xilinx FSBL I was able to get RTEMS to properly start up and wake up both processors.

If anyone in the future has questions on this please let me know and I'll try to provide a better explanation if this one doesn't make sense.


From: devel <devel-bounces at rtems.org> On Behalf Of Misra, Avinash
Sent: Monday, December 17, 2018 4:37 PM
To: rtems-devel at rtems.org <devel at rtems.org>
Subject: Zynq SMP CPU0 Not Waking CPU1


I'm attempting to get SMP running on my Zynq board and am having an issue. It would appear that during CPU Initialization CPU0 initializes and then loops through _ARM_Data_memory_barrier waiting to receive a message from CPU1 before starting. The issue is that it would appear that it never receives the message from CPU1. I am currently able to get around this by manually waking up CPU1 through the Xilinx SDK but am not sure why CPU1 is not automatically starting. Have I missed a step?

[cid:image001.png at 01D49628.798B2F50]

Avi Misra

JHU Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, MD 20723
Baltimore: (443) 778-8362
Washington: (240) 228-8362
Cell: (714) 594-8239

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