SMP Testing of RISC-V

[Sebastian Huber]

On 21/05/2019 16:26, Joel Sherrill wrote:
>
>
> On Mon, May 20, 2019 at 11:23 PM Sebastian Huber 
> <sebastian.huber at embedded-brains.de 
> <mailto:sebastian.huber at embedded-brains.de>> wrote:
>
>     On 20/05/2019 20:23, Joel Sherrill wrote:
>     > Hi
>     >
>     > I can't seem to find the number of cores the RISC-V port has
>     been tested
>     > on. I couldn't even find test results for riscv RTEMS in the
>     archives.
>     > Info
>     > appreciated.
>
>     I tested with up to two cores and mostly using a 64-bit target. It
>     should work on up to 32 cores.
>
>
> Was this on hardware or qemu?

Hardware, RISC-V SMP was not supported on Qemu at that time.

>
>     >
>     > I see rtems-tester configurations for spike and sis. Are there
>     any for
>     > qemu?
>     > I thought qemu worked for RISC-V even if it had to be a special
>     version.
>
>     The configurations without the _spike use Qemu.
>
>
> Thanks. Is this one of the RSB qemu configurations?
>
> I am trying to figure out which BSP variants are expected to work with
> which simulators and in what configurations so I can add them to the
> semi-automated test sweep script I have been trying to run once a week.
>
> Spike in the RSB doesn't build for me.
>
> So I haven't found a combination of BSP and simulator to add.
>
> Suggestions appreciated.

It worked at some point in time:

https://lists.rtems.org/pipermail/build/2018-July/000771.html

Using Jiri Gaislers SIS for RISC-V simulation would be probably the most 
useful.

-- 
Sebastian Huber, embedded brains GmbH

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