sparc-erc32 testsuites failures

[Joel Sherrill]

On Sun, Nov 17, 2019, 1:42 PM Niteesh <gsnb.gn at gmail.com> wrote:

> The test's for the sparc-erc32 BSP fail's. when running rtems-test for
> this particular BSP it fails for almost all test cases, the error message:
>
> *undefined target command: "sim"*
>
> I think it's because the tests are run using sparc-rtems-gdb, but the sis
> target was disabled in this commit:
>
> https://git.rtems.org/rtems-source-builder/commit/?id=abc540105d10ddc9cad7de3c7ac0a9aa209ac828
> and was moved to use the standalone sparc-rtems-sis. I think this is what
> is causing the problem, but not so sure. Can someone guide on how to fix
> this?
>

The instructions are out of date by a couple of months. The SPARC
Instruction Simulator (sis) has seen significant enhancements and it's now
a standalone program. It is not enabled as a built-in with gdb because
that's some very old version of sis. The new version has symmetric
multiprocessing and support for the RISC-V.

Those instructions worked for a LONG time but need to be updated to reflect
the recent changes with SIS.

If you used rtems-tester, it should work. And looking at the .ini file for
this bsp will sure you have to just run programs with the simulator. My
recollection is that by adding -gdb argument, you can attached to it as a
remote debugger.

>
> BTW I know it's a way too early for GSOC but I have anyway attached the
> patch for hello world.
>

What type projects are you interested in?

>
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