xilinx_zynq_zc702 vs. xilinx_zynq_zc706 memory map

[Sebastian Huber]

Hello,

why is the ZYNQ_RAM_ORIGIN different in these two BSP variants?

AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
       [ZYNQ_RAM_ORIGIN="0x00100000"
        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])

AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
       [ZYNQ_RAM_ORIGIN="0x00400000"
        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
        ZYNQ_RAM_MMU_LENGTH="16k"
        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
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E-Mail  : sebastian.huber at embedded-brains.de
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