xilinx_zynq_zc702 vs. xilinx_zynq_zc706 memory map

[Thomas Doerfler]

Hi,

most likely the RAM areas have been mapped to the lowest-possible
non-NULL address, and they can be mapped to an address boundary matching
the RAM size. zc702 has a 1MByte ram, mapped to the 1MByte boundary,
zc706 has a 4MByte RAM mapped to the 4MByte boundary.

Having an identical starting address for all possible zynqs would mean to
- identify the biggest ever possible RAM size
- modify the zynq initialization for all boards.

Do we have a problem with the different starting addresses?

wkr,

Thomas.

Am 23.10.19 um 13:47 schrieb Sebastian Huber:
> Hello,
> 
> why is the ZYNQ_RAM_ORIGIN different in these two BSP variants?
> 
> AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
>       [ZYNQ_RAM_ORIGIN="0x00100000"
>        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
>        ZYNQ_RAM_MMU_LENGTH="16k"
>        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
>        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
>        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
>        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
>        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
>        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
> 
> AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
>       [ZYNQ_RAM_ORIGIN="0x00400000"
>        ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
>        ZYNQ_RAM_MMU_LENGTH="16k"
>        ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
>        ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
>        ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
>        ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
>        ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
>        ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
> 

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