[PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()

[Kinsey Moore]

-----Original Message-----
From: Sebastian Huber <sebastian.huber at embedded-brains.de> 
Sent: Wednesday, December 9, 2020 23:46
To: Kinsey Moore <kinsey.moore at oarcorp.com>; devel at rtems.org
Subject: Re: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()

> On 10/12/2020 00:26, Kinsey Moore wrote:
>
>> -----Original Message-----
>> From: devel<devel-bounces at rtems.org>  On Behalf Of Sebastian Huber
>> Sent: Wednesday, December 9, 2020 10:33 To:devel at rtems.org
>> Subject: [PATCH v2] bsps: Fix GICv3 arm_gic_trigger_sgi()
>>
>>> diff --git a/bsps/shared/dev/irq/arm-gicv3.c 
>>> b/bsps/shared/dev/irq/arm-gicv3.c index db10371c72..569c7610c4 100644
>>> --- a/bsps/shared/dev/irq/arm-gicv3.c
>>> +++ b/bsps/shared/dev/irq/arm-gicv3.c
>>> @@ -356,7 +356,7 @@ void arm_gic_trigger_sgi(
>>>     uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
>>>                    | ICC_SGIR_INTID(vector)
>>>                    | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
>>> -                 | ICC_SGIR_CPU_TARGET_LIST(1);
>>> +                 | ICC_SGIR_CPU_TARGET_LIST(targets);
>> I think my processor filter todo just above this code will need to be addressed along with this change for correct behavior on non-core 0 runs of tm27.
> Yes, I thought about non-core 0 test runs too, however, I guess a lot more things will pop up if someone does this the first time. We could replace the 1 with an 1 << (arm_cp15_get_multiprocessor_affinity() & 0xff).

That sounds good for the time being. I'll work on a patch to address the filter issues.

Kinsey