Raspberry Pi Pico

Joel Sherrill joel at rtems.org
Thu Jan 21 15:44:30 UTC 2021


Is a BSP for this feasible? If it is feasible, is is a GSoC size project?

It is an M0+ with 264k SRAM. Although I'm not sure what six independent
banks does to the amount of RAM for programs?


I can see the M0+ support in RTEMS being a broad issue and the memory
layout being another but the datasheet seems to show the memory as one


Feature list:

Dual ARM Cortex-M0+ @ 133MHz
264kB on-chip SRAM in six independent banks
Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus
DMA controller
Fully-connected AHB crossbar
Interpolator and integer divider peripherals
On-chip programmable LDO to generate core voltage
2 on-chip PLLs to generate USB and core clocks
30 GPIO pins, 4 of which can be used as analog inputs
2 SPI controllers
2 I2C controllers
16 PWM channels
USB 1.1 controller and PHY, with host and device support
8 PIO state machines

Not our problem but I don't see obvious details on hooking up a JTAG but if
someone does a BSP, that will be an issue.
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