[PATCH 10/10] sparc: Simplify trap table initialization
Gedare Bloom
gedare at rtems.org
Wed Jun 23 20:42:20 UTC 2021
This patch set looks ok, but it touches a lot of assembly. Try to
ensure all variants have been thoroughly tested, including the
different ways to setup the FPU on sparc (lazy, hard/soft), with SMP,
and Profiling.
On Wed, Jun 23, 2021 at 12:50 AM Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
>
> Move _ISR_Handler() to a separate file since it is now only used if a handler
> is installed by _CPU_ISR_install_raw_handler().
>
> Statically initialize the traps for external interrupts to use the new
> _SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
> installed by rtems_interrupt_handler_install() via the BSP-provided
> _SPARC_Interrupt_dispatch().
>
> Since the trap table is now fully statically initialized, there is no longer a
> dependency on the Cache Manager in the default configuration.
>
> Update #4458.
> ---
> bsps/sparc/erc32/include/bsp.h | 6 -
> bsps/sparc/erc32/start/bspstart.c | 15 +-
> bsps/sparc/leon2/include/bsp.h | 6 -
> bsps/sparc/leon2/start/bspstart.c | 2 +-
> bsps/sparc/leon3/include/bsp.h | 6 -
> bsps/sparc/leon3/start/bspsmp.c | 24 +-
> bsps/sparc/leon3/start/bspstart.c | 34 +-
> bsps/sparc/shared/irq/bsp_isr_handler.c | 27 +-
> bsps/sparc/shared/irq/irq-shared.c | 21 -
> bsps/sparc/shared/start/start.S | 39 +-
> cpukit/Makefile.am | 1 +
> cpukit/score/cpu/sparc/cpu_asm.S | 64 +-
> .../score/cpu/sparc/include/rtems/score/cpu.h | 8 +-
> cpukit/score/cpu/sparc/sparc-isr-handler.S | 620 ++++++++++++++++++
> spec/build/cpukit/cpusparc.yml | 1 +
> 15 files changed, 704 insertions(+), 170 deletions(-)
> create mode 100644 cpukit/score/cpu/sparc/sparc-isr-handler.S
>
> diff --git a/bsps/sparc/erc32/include/bsp.h b/bsps/sparc/erc32/include/bsp.h
> index 7fb2fa9d72..fd453fb6c2 100644
> --- a/bsps/sparc/erc32/include/bsp.h
> +++ b/bsps/sparc/erc32/include/bsp.h
> @@ -95,12 +95,6 @@ void BSP_fatal_exit(uint32_t error);
> /* Interrupt Service Routine (ISR) pointer */
> typedef void (*bsp_shared_isr)(void *arg);
>
> -/* Initializes the Shared System Interrupt service */
> -extern void BSP_shared_interrupt_init(void);
> -
> -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */
> -void bsp_isr_handler(rtems_vector_number vector);
> -
> /* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple
> * interrupt handlers may use the same IRQ number, all ISRs will be called
> * when an interrupt on that line is fired.
> diff --git a/bsps/sparc/erc32/start/bspstart.c b/bsps/sparc/erc32/start/bspstart.c
> index d56d3b2ff2..1979c68308 100644
> --- a/bsps/sparc/erc32/start/bspstart.c
> +++ b/bsps/sparc/erc32/start/bspstart.c
> @@ -12,22 +12,15 @@
>
> #include <bsp.h>
> #include <bsp/bootcard.h>
> +#include <bsp/irq-generic.h>
> #include <rtems/sysinit.h>
>
> /*
> - * Called just before drivers are initialized. Is used to initialize shared
> - * interrupt handling.
> + * Initialize shared interrupt handling, must be done after IRQ controller has
> + * been found and initialized.
> */
> -static void erc32_pre_driver_hook( void )
> -{
> - /* Initialize shared interrupt handling, must be done after IRQ
> - * controller has been found and initialized.
> - */
> - BSP_shared_interrupt_init();
> -}
> -
> RTEMS_SYSINIT_ITEM(
> - erc32_pre_driver_hook,
> + bsp_interrupt_initialize,
> RTEMS_SYSINIT_BSP_PRE_DRIVERS,
> RTEMS_SYSINIT_ORDER_MIDDLE
> );
> diff --git a/bsps/sparc/leon2/include/bsp.h b/bsps/sparc/leon2/include/bsp.h
> index bdd9c1ca70..510262206b 100644
> --- a/bsps/sparc/leon2/include/bsp.h
> +++ b/bsps/sparc/leon2/include/bsp.h
> @@ -119,12 +119,6 @@ void BSP_fatal_exit(uint32_t error);
> /* Interrupt Service Routine (ISR) pointer */
> typedef void (*bsp_shared_isr)(void *arg);
>
> -/* Initializes the Shared System Interrupt service */
> -extern void BSP_shared_interrupt_init(void);
> -
> -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */
> -void bsp_isr_handler(rtems_vector_number vector);
> -
> /* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple
> * interrupt handlers may use the same IRQ number, all ISRs will be called
> * when an interrupt on that line is fired.
> diff --git a/bsps/sparc/leon2/start/bspstart.c b/bsps/sparc/leon2/start/bspstart.c
> index 8ffd0aa2e7..e90cfad5a8 100644
> --- a/bsps/sparc/leon2/start/bspstart.c
> +++ b/bsps/sparc/leon2/start/bspstart.c
> @@ -111,7 +111,7 @@ static void leon2_pre_driver_hook( void )
> /* Initialize shared interrupt handling, must be done after IRQ
> * controller has been found and initialized.
> */
> - BSP_shared_interrupt_init();
> + bsp_interrupt_initialize();
>
> #ifdef RTEMS_DRVMGR_STARTUP
> leon2_root_register(&leon2_bus_config, &leon2_amba_res);
> diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h
> index 82f1f9f8ac..cb08764eae 100644
> --- a/bsps/sparc/leon3/include/bsp.h
> +++ b/bsps/sparc/leon3/include/bsp.h
> @@ -139,12 +139,6 @@ void rtems_bsp_delay(int usecs);
> /* Interrupt Service Routine (ISR) pointer */
> typedef void (*bsp_shared_isr)(void *arg);
>
> -/* Initializes the Shared System Interrupt service */
> -extern void BSP_shared_interrupt_init(void);
> -
> -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */
> -void bsp_isr_handler(rtems_vector_number vector);
> -
> /* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple
> * interrupt handlers may use the same IRQ number, all ISRs will be called
> * when an interrupt on that line is fired.
> diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c
> index c73c3fd5d0..f2749bfa06 100644
> --- a/bsps/sparc/leon3/start/bspsmp.c
> +++ b/bsps/sparc/leon3/start/bspsmp.c
> @@ -18,6 +18,7 @@
> #include <bsp/fatal.h>
> #include <leon.h>
> #include <rtems/bspIo.h>
> +#include <rtems/sysinit.h>
> #include <rtems/score/assert.h>
> #include <rtems/score/smpimpl.h>
> #include <stdlib.h>
> @@ -55,13 +56,10 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
> _SMP_Start_multitasking_on_secondary_processor(cpu_self);
> }
>
> -uint32_t _CPU_SMP_Initialize( void )
> +static void leon3_install_inter_processor_interrupt( void )
> {
> rtems_status_code sc;
>
> - if ( !leon3_data_cache_snooping_enabled() )
> - bsp_fatal( LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR );
> -
> sc = rtems_interrupt_handler_install(
> LEON3_mp_irq,
> "IPI",
> @@ -70,6 +68,16 @@ uint32_t _CPU_SMP_Initialize( void )
> NULL
> );
> _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
> +}
> +
> +uint32_t _CPU_SMP_Initialize( void )
> +{
> + if ( !leon3_data_cache_snooping_enabled() )
> + bsp_fatal( LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR );
> +
> +#if !defined(RTEMS_DRVMGR_STARTUP)
> + leon3_install_inter_processor_interrupt();
> +#endif
>
> return leon3_get_cpu_count(LEON3_IrqCtrl_Regs);
> }
> @@ -102,3 +110,11 @@ void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
> /* send interrupt to destination CPU */
> LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_mp_irq;
> }
> +
> +#if defined(RTEMS_DRVMGR_STARTUP)
> +RTEMS_SYSINIT_ITEM(
> + leon3_install_inter_processor_interrupt,
> + RTEMS_SYSINIT_DRVMGR_LEVEL_1,
> + RTEMS_SYSINIT_ORDER_LAST_BUT_4
> +);
> +#endif
> diff --git a/bsps/sparc/leon3/start/bspstart.c b/bsps/sparc/leon3/start/bspstart.c
> index 69ff519189..75042e4c20 100644
> --- a/bsps/sparc/leon3/start/bspstart.c
> +++ b/bsps/sparc/leon3/start/bspstart.c
> @@ -20,6 +20,7 @@
> */
>
> #include <bsp.h>
> +#include <bsp/irq-generic.h>
> #include <leon.h>
> #include <bsp/bootcard.h>
> #include <rtems/sysinit.h>
> @@ -66,6 +67,10 @@ static inline int set_snooping(void)
> void bsp_start( void )
> {
> CPU_SPARC_HAS_SNOOPING = set_snooping();
> +
> +#ifndef RTEMS_DRVMGR_STARTUP
> + bsp_interrupt_initialize();
> +#endif
> }
>
> static void leon3_cpu_index_init(void)
> @@ -84,38 +89,13 @@ RTEMS_SYSINIT_ITEM(
> RTEMS_SYSINIT_ORDER_FIRST
> );
>
> -static void leon3_interrupt_common_init( void )
> -{
> - /* Initialize shared interrupt handling, must be done after IRQ
> - * controller has been found and initialized.
> - */
> - BSP_shared_interrupt_init();
> -}
> -
> -/*
> - * Called just before drivers are initialized. Is used to initialize shared
> - * interrupt handling.
> - */
> -static void leon3_pre_driver_hook( void )
> -{
> -#ifndef RTEMS_DRVMGR_STARTUP
> - leon3_interrupt_common_init();
> -#endif
> -}
> -
> -RTEMS_SYSINIT_ITEM(
> - leon3_pre_driver_hook,
> - RTEMS_SYSINIT_BSP_PRE_DRIVERS,
> - RTEMS_SYSINIT_ORDER_MIDDLE
> -);
> -
> -#ifdef RTEMS_DRVMGR_STARTUP
> /*
> * Initialize shared interrupt handling, must be done after IRQ controller has
> * been found and initialized.
> */
> +#ifdef RTEMS_DRVMGR_STARTUP
> RTEMS_SYSINIT_ITEM(
> - leon3_interrupt_common_init,
> + bsp_interrupt_initialize,
> RTEMS_SYSINIT_DRVMGR_LEVEL_1,
> RTEMS_SYSINIT_ORDER_LAST_BUT_5
> );
> diff --git a/bsps/sparc/shared/irq/bsp_isr_handler.c b/bsps/sparc/shared/irq/bsp_isr_handler.c
> index a4d33b0932..2616b5caae 100644
> --- a/bsps/sparc/shared/irq/bsp_isr_handler.c
> +++ b/bsps/sparc/shared/irq/bsp_isr_handler.c
> @@ -8,28 +8,19 @@
> *
> */
>
> -#include <rtems.h>
> #include <bsp.h>
> #include <bsp/irq-generic.h>
>
> -static inline void bsp_dispatch_irq(int irq)
> -{
> - bsp_interrupt_handler_entry *e =
> - &bsp_interrupt_handler_table[bsp_interrupt_handler_index(irq)];
> -
> - while (e != NULL) {
> - (*e->handler)(e->arg);
> - e = e->next;
> - }
> -}
> -
> -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */
> -void bsp_isr_handler(rtems_vector_number vector)
> +/*
> + * This function is called directly from _SPARC_Interrupt_trap() for
> + * traps 0x10 to 0x1F which correspond to IRQ 0 to 15 respectively.
> + */
> +void _SPARC_Interrupt_dispatch( uint32_t irq )
> {
> - int irq = vector - 0x10;
> + bsp_interrupt_assert( irq < BSP_INTERRUPT_VECTOR_COUNT );
>
> - /* Let BSP fixup and/or handle incomming IRQ */
> - irq = bsp_irq_fixup(irq);
> + /* Let BSP fixup and/or handle incoming IRQ */
> + irq = bsp_irq_fixup( irq );
>
> - bsp_dispatch_irq(irq);
> + bsp_interrupt_handler_dispatch_unchecked( irq );
> }
> diff --git a/bsps/sparc/shared/irq/irq-shared.c b/bsps/sparc/shared/irq/irq-shared.c
> index e0ac7d7f06..a127ab64c2 100644
> --- a/bsps/sparc/shared/irq/irq-shared.c
> +++ b/bsps/sparc/shared/irq/irq-shared.c
> @@ -37,27 +37,6 @@ static inline int bsp_irq_cpu(int irq)
> }
> #endif
>
> -/* Initialize interrupts */
> -void BSP_shared_interrupt_init(void)
> -{
> - rtems_vector_number vector;
> - rtems_isr_entry previous_isr;
> - int i;
> -
> - for (i=0; i <= BSP_INTERRUPT_VECTOR_MAX_STD; i++) {
> -#if defined(LEON3) && (defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING))
> - /* Don't install IRQ handler on IPI interrupt */
> - if (i == LEON3_mp_irq)
> - continue;
> -#endif
> - vector = SPARC_ASYNCHRONOUS_TRAP(i) + 0x10;
> - rtems_interrupt_catch(bsp_isr_handler, vector, &previous_isr);
> - }
> -
> - /* Initalize interrupt support */
> - bsp_interrupt_initialize();
> -}
> -
> /* Callback from bsp_interrupt_initialize() */
> rtems_status_code bsp_interrupt_facility_initialize(void)
> {
> diff --git a/bsps/sparc/shared/start/start.S b/bsps/sparc/shared/start/start.S
> index cd43f08f01..45bd145d4a 100644
> --- a/bsps/sparc/shared/start/start.S
> +++ b/bsps/sparc/shared/start/start.S
> @@ -32,6 +32,13 @@
> TRAP_SYM(_vector):; \
> TRAP(_vector, _SPARC_Bad_trap)
>
> +/*
> + * External interrupt trap
> + */
> +#define ISR_TRAP(_vector) \
> + TRAP_SYM(_vector):; \
> + TRAP(_vector - 0x10, _SPARC_Interrupt_trap)
> +
> /*
> * System call optimized trap table entry
> */
> @@ -128,27 +135,27 @@ TRAP_SYM(0x06):
> BAD_TRAP(0x0d) ! 0D undefined
> BAD_TRAP(0x0e) ! 0E undefined
> BAD_TRAP(0x0f) ! 0F undefined
> - BAD_TRAP(0x10) ! 10 undefined
>
> /*
> * External interrupt traps
> */
>
> - BAD_TRAP(0x11) ! 11 external interrupt 1
> - BAD_TRAP(0x12) ! 12 external interrupt 2
> - BAD_TRAP(0x13) ! 13 external interrupt 3
> - BAD_TRAP(0x14) ! 14 external interrupt 4
> - BAD_TRAP(0x15) ! 15 external interrupt 5
> - BAD_TRAP(0x16) ! 16 external interrupt 6
> - BAD_TRAP(0x17) ! 17 external interrupt 7
> - BAD_TRAP(0x18) ! 18 external interrupt 8
> - BAD_TRAP(0x19) ! 19 external interrupt 9
> - BAD_TRAP(0x1a) ! 1A external interrupt 10
> - BAD_TRAP(0x1b) ! 1B external interrupt 11
> - BAD_TRAP(0x1c) ! 1C external interrupt 12
> - BAD_TRAP(0x1d) ! 1D external interrupt 13
> - BAD_TRAP(0x1e) ! 1E external interrupt 14
> - BAD_TRAP(0x1f) ! 1F external interrupt 15
> + ISR_TRAP(0x10) ! 10 undefined
> + ISR_TRAP(0x11) ! 11 external interrupt 1
> + ISR_TRAP(0x12) ! 12 external interrupt 2
> + ISR_TRAP(0x13) ! 13 external interrupt 3
> + ISR_TRAP(0x14) ! 14 external interrupt 4
> + ISR_TRAP(0x15) ! 15 external interrupt 5
> + ISR_TRAP(0x16) ! 16 external interrupt 6
> + ISR_TRAP(0x17) ! 17 external interrupt 7
> + ISR_TRAP(0x18) ! 18 external interrupt 8
> + ISR_TRAP(0x19) ! 19 external interrupt 9
> + ISR_TRAP(0x1a) ! 1A external interrupt 10
> + ISR_TRAP(0x1b) ! 1B external interrupt 11
> + ISR_TRAP(0x1c) ! 1C external interrupt 12
> + ISR_TRAP(0x1d) ! 1D external interrupt 13
> + ISR_TRAP(0x1e) ! 1E external interrupt 14
> + ISR_TRAP(0x1f) ! 1F external interrupt 15
>
> BAD_TRAP(0x20) ! 20 undefined
> BAD_TRAP(0x21) ! 21 undefined
> diff --git a/cpukit/Makefile.am b/cpukit/Makefile.am
> index 83c14cd2ab..c83167668d 100644
> --- a/cpukit/Makefile.am
> +++ b/cpukit/Makefile.am
> @@ -1623,6 +1623,7 @@ librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-validate.S
> librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-volatile-clobber.S
> librtemscpu_a_SOURCES += score/cpu/sparc/sparc-counter-asm.S
> librtemscpu_a_SOURCES += score/cpu/sparc/sparc-exception-frame-print.c
> +librtemscpu_a_SOURCES += score/cpu/sparc/sparc-isr-handler.S
> librtemscpu_a_SOURCES += score/cpu/sparc/sparc-isr-install.c
> librtemscpu_a_SOURCES += score/cpu/sparc/syscall.S
> librtemscpu_a_SOURCES += score/cpu/sparc/window.S
> diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S
> index 16f5c70206..45d1495af7 100644
> --- a/cpukit/score/cpu/sparc/cpu_asm.S
> +++ b/cpukit/score/cpu/sparc/cpu_asm.S
> @@ -295,7 +295,7 @@ SYM(_CPU_Context_restore):
> mov %i0, %o1 ! in the delay slot
>
> /*
> - * void _ISR_Handler()
> + * void _SPARC_Interrupt_trap()
> *
> * This routine provides the RTEMS interrupt management.
> *
> @@ -305,28 +305,14 @@ SYM(_CPU_Context_restore):
> * l0 = PSR
> * l1 = PC
> * l2 = nPC
> - * l3 = trap type
> + * l3 = interrupt vector number (this is not the trap type)
> *
> - * NOTE: By an executive defined convention, trap type is between 0 and 255 if
> - * it is an asynchonous trap and 256 and 511 if it is synchronous.
> + * NOTE: This trap handler is intended to service external interrupts.
> */
>
> .align 4
> - PUBLIC(_ISR_Handler)
> -SYM(_ISR_Handler):
> - /*
> - * Fix the return address for synchronous traps.
> - */
> -
> - andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
> - ! Is this a synchronous trap?
> - be,a win_ovflow ! No, then skip the adjustment
> - nop ! DELAY
> - mov %l1, %l6 ! save trapped pc for debug info
> - mov %l2, %l1 ! do not return to the instruction
> - add %l2, 4, %l2 ! indicated
> -
> -win_ovflow:
> + PUBLIC(_SPARC_Interrupt_trap)
> +SYM(_SPARC_Interrupt_trap):
> /*
> * Save the globals this block uses.
> *
> @@ -413,7 +399,7 @@ dont_do_the_window:
> * includes a regular minimum stack frame which will be used if
> * needed by register window overflow and underflow handlers.
> *
> - * REGISTERS SAME AS AT _ISR_Handler
> + * REGISTERS SAME AS AT _SPARC_Interrupt_trap()
> */
>
> sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
> @@ -439,9 +425,6 @@ dont_do_the_window:
>
> rd %y, %g1
> st %g1, [%sp + ISF_Y_OFFSET] ! save y
> - st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
> -
> - mov %sp, %o1 ! 2nd arg to ISR Handler
>
> /*
> * Increment ISR nest level and Thread dispatch disable level.
> @@ -520,26 +503,16 @@ dont_switch_stacks:
> sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
>
> /*
> - * Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
> - * set the PIL in the %psr to mask off interrupts with lower priority.
> + * Set the PIL in the %psr to mask off interrupts with lower priority.
> * The original %psr in %l0 is not modified since it will be restored
> * when the interrupt handler returns.
> */
>
> mov %l0, %g5
> - and %l3, 0x0ff, %g4
> - subcc %g4, 0x11, %g0
> - bl dont_fix_pil
> - subcc %g4, 0x1f, %g0
> - bg dont_fix_pil
> - sll %g4, 8, %g4
> + sll %l3, 8, %g4
> and %g4, SPARC_PSR_PIL_MASK, %g4
> andn %l0, SPARC_PSR_PIL_MASK, %g5
> - ba pil_fixed
> or %g4, %g5, %g5
> -dont_fix_pil:
> - or %g5, SPARC_PSR_PIL_MASK, %g5
> -pil_fixed:
>
> #if SPARC_HAS_FPU == 1
> /*
> @@ -552,23 +525,10 @@ pil_fixed:
> wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
>
> /*
> - * Vector to user's handler.
> - *
> - * NOTE: TBR may no longer have vector number in it since
> - * we just enabled traps. It is definitely in l3.
> + * Call _SPARC_Interrupt_dispatch( %l3 )
> */
> -
> - sethi %hi(SYM(_ISR_Vector_table)), %g4
> - or %g4, %lo(SYM(_ISR_Vector_table)), %g4
> - and %l3, 0xFF, %g5 ! remove synchronous trap indicator
> - sll %g5, 2, %g5 ! g5 = offset into table
> - ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
> -
> -
> - ! o1 = 2nd arg = address of the ISF
> - ! WAS LOADED WHEN ISF WAS SAVED!!!
> mov %l3, %o0 ! o0 = 1st arg = vector number
> - call %g4
> + call SYM(_SPARC_Interrupt_dispatch)
> #if defined(RTEMS_PROFILING)
> mov %o5, %l3 ! save interrupt entry instant
> #else
> @@ -780,8 +740,8 @@ isr_dispatch:
> * The CWP in place at this point may be different from
> * that which was in effect at the beginning of the ISR if we
> * have been context switched between the beginning of this invocation
> - * of _ISR_Handler and this point. Thus the CWP and WIM should
> - * not be changed back to their values at ISR entry time. Any
> + * of _SPARC_Interrupt_trap() and this point. Thus the CWP and WIM
> + * should not be changed back to their values at ISR entry time. Any
> * changes to the PSR must preserve the CWP.
> */
>
> diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
> index f3f50d4f78..0abc929c54 100644
> --- a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
> @@ -743,9 +743,13 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
>
> #ifndef ASM
>
> -/*
> - * ISR handler macros
> +/**
> + * @brief Dispatches the installed interrupt handlers.
> + *
> + * @param irq is the interrupt vector number of the external interrupt ranging
> + * from 0 to 15. This is not a trap number.
> */
> +void _SPARC_Interrupt_dispatch( uint32_t irq );
>
> /**
> * Disable all interrupts for a critical section. The previous
> diff --git a/cpukit/score/cpu/sparc/sparc-isr-handler.S b/cpukit/score/cpu/sparc/sparc-isr-handler.S
> new file mode 100644
> index 0000000000..068fad1e84
> --- /dev/null
> +++ b/cpukit/score/cpu/sparc/sparc-isr-handler.S
> @@ -0,0 +1,620 @@
> +/*
> + * This file contains the basic algorithms for all assembly code used
> + * in an specific CPU port of RTEMS. These algorithms must be implemented
> + * in assembly language.
> + *
> + * COPYRIGHT (c) 1989-2011.
> + * On-Line Applications Research Corporation (OAR).
> + *
> + * Copyright (c) 2014, 2017 embedded brains GmbH
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + *
> + * Ported to ERC32 implementation of the SPARC by On-Line Applications
> + * Research Corporation (OAR) under contract to the European Space
> + * Agency (ESA).
> + *
> + * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
> + * European Space Agency.
> + */
> +
> +#include <rtems/asm.h>
> +#include <rtems/score/percpu.h>
> +#include <libcpu/grlib-tn-0018.h>
> +
> +/*
> + * void _ISR_Handler()
> + *
> + * This routine provides the RTEMS interrupt management.
> + *
> + * We enter this handler from the 4 instructions in the trap table with
> + * the following registers assumed to be set as shown:
> + *
> + * l0 = PSR
> + * l1 = PC
> + * l2 = nPC
> + * l3 = trap type
> + *
> + * NOTE: By an executive defined convention, trap type is between 0 and 255 if
> + * it is an asynchonous trap and 256 and 511 if it is synchronous.
> + */
> +
> + .align 4
> + PUBLIC(_ISR_Handler)
> +SYM(_ISR_Handler):
> + /*
> + * Fix the return address for synchronous traps.
> + */
> +
> + andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
> + ! Is this a synchronous trap?
> + be,a win_ovflow ! No, then skip the adjustment
> + nop ! DELAY
> + mov %l1, %l6 ! save trapped pc for debug info
> + mov %l2, %l1 ! do not return to the instruction
> + add %l2, 4, %l2 ! indicated
> +
> +win_ovflow:
> + /*
> + * Save the globals this block uses.
> + *
> + * These registers are not restored from the locals. Their contents
> + * are saved directly from the locals into the ISF below.
> + */
> +
> + mov %g4, %l4 ! save the globals this block uses
> + mov %g5, %l5
> +
> + /*
> + * When at a "window overflow" trap, (wim == (1 << cwp)).
> + * If we get here like that, then process a window overflow.
> + */
> +
> + rd %wim, %g4
> + srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
> + ! are LS 5 bits ; how convenient :)
> + cmp %g5, 1 ! Is this an invalid window?
> + bne dont_do_the_window ! No, then skip all this stuff
> + ! we are using the delay slot
> +
> + /*
> + * The following is same as a 1 position right rotate of WIM
> + */
> +
> + srl %g4, 1, %g5 ! g5 = WIM >> 1
> + sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
> + ! g4 = WIM << (Number Windows - 1)
> + or %g4, %g5, %g4 ! g4 = (WIM >> 1) |
> + ! (WIM << (Number Windows - 1))
> +
> + /*
> + * At this point:
> + *
> + * g4 = the new WIM
> + * g5 is free
> + */
> +
> + /*
> + * Since we are tinkering with the register windows, we need to
> + * make sure that all the required information is in global registers.
> + */
> +
> + save ! Save into the window
> + wr %g4, 0, %wim ! WIM = new WIM
> + nop ! delay slots
> + nop
> + nop
> +
> + /*
> + * Now save the window just as if we overflowed to it.
> + */
> +
> + std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> +
> + std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
> + SPARC_LEON3FT_B2BST_NOP
> + std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
> +
> + restore
> + nop
> +
> +dont_do_the_window:
> + /*
> + * Global registers %g4 and %g5 are saved directly from %l4 and
> + * %l5 directly into the ISF below.
> + */
> +
> + /*
> + * Save the state of the interrupted task -- especially the global
> + * registers -- in the Interrupt Stack Frame. Note that the ISF
> + * includes a regular minimum stack frame which will be used if
> + * needed by register window overflow and underflow handlers.
> + *
> + * REGISTERS SAME AS AT _ISR_Handler
> + */
> +
> + sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
> + ! make space for ISF
> +
> + std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
> + SPARC_LEON3FT_B2BST_NOP
> + st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
> + st %g1, [%sp + ISF_G1_OFFSET] ! save g1
> + std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
> + SPARC_LEON3FT_B2BST_NOP
> + std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
> + SPARC_LEON3FT_B2BST_NOP
> + st %g7, [%sp + ISF_G7_OFFSET] ! save g7
> +
> + std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
> + SPARC_LEON3FT_B2BST_NOP
> + std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
> + SPARC_LEON3FT_B2BST_NOP
> + std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
> + SPARC_LEON3FT_B2BST_NOP
> + std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
> +
> + rd %y, %g1
> + st %g1, [%sp + ISF_Y_OFFSET] ! save y
> + st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
> +
> + mov %sp, %o1 ! 2nd arg to ISR Handler
> +
> + /*
> + * Increment ISR nest level and Thread dispatch disable level.
> + *
> + * Register usage for this section:
> + *
> + * l6 = _Thread_Dispatch_disable_level value
> + * l7 = _ISR_Nest_level value
> + *
> + * NOTE: It is assumed that l6 - l7 will be preserved until the ISR
> + * nest and thread dispatch disable levels are unnested.
> + */
> +
> + ld [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
> + ld [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
> +
> + add %l7, 1, %l7
> + st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
> + SPARC_LEON3FT_B2BST_NOP
> +
> + add %l6, 1, %l6
> + st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
> +
> +#if SPARC_HAS_FPU == 1
> + /*
> + * We cannot use an intermediate value for operations with the PSR[EF]
> + * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
> + */
> + sethi %hi(SPARC_PSR_EF_MASK), %l5
> +#endif
> +
> + /*
> + * If ISR nest level was zero (now 1), then switch stack.
> + */
> +
> + mov %sp, %fp
> + subcc %l7, 1, %l7 ! outermost interrupt handler?
> + bnz dont_switch_stacks ! No, then do not switch stacks
> +
> +#if defined(RTEMS_PROFILING)
> + sethi %hi(_SPARC_Counter), %o5
> + ld [%o5 + %lo(_SPARC_Counter)], %l4
> + call %l4
> + nop
> + mov %o0, %o5
> +#else
> + nop
> +#endif
> +
> + ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
> +
> +#if SPARC_HAS_FPU == 1
> + /*
> + * Test if the interrupted thread uses the floating point unit
> + * (PSR[EF] == 1). In case it uses the floating point unit, then store
> + * the floating point status register. This has the side-effect that
> + * all pending floating point operations complete before the store
> + * completes. The PSR[EF] bit is restored after the call to the
> + * interrupt handler. Thus post-switch actions (e.g. signal handlers)
> + * and context switch extensions may still corrupt the floating point
> + * context.
> + */
> + andcc %l0, %l5, %g0
> + beq dont_switch_stacks
> + nop
> + st %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
> +#endif
> +
> +dont_switch_stacks:
> + /*
> + * Make sure we have a place on the stack for the window overflow
> + * trap handler to write into. At this point it is safe to
> + * enable traps again.
> + */
> +
> + sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
> +
> + /*
> + * Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
> + * set the PIL in the %psr to mask off interrupts with lower priority.
> + * The original %psr in %l0 is not modified since it will be restored
> + * when the interrupt handler returns.
> + */
> +
> + mov %l0, %g5
> + and %l3, 0x0ff, %g4
> + subcc %g4, 0x11, %g0
> + bl dont_fix_pil
> + subcc %g4, 0x1f, %g0
> + bg dont_fix_pil
> + sll %g4, 8, %g4
> + and %g4, SPARC_PSR_PIL_MASK, %g4
> + andn %l0, SPARC_PSR_PIL_MASK, %g5
> + ba pil_fixed
> + or %g4, %g5, %g5
> +dont_fix_pil:
> + or %g5, SPARC_PSR_PIL_MASK, %g5
> +pil_fixed:
> +
> +#if SPARC_HAS_FPU == 1
> + /*
> + * Clear the PSR[EF] bit of the interrupted context to ensure that
> + * interrupt service routines cannot corrupt the floating point context.
> + */
> + andn %g5, %l5, %g5
> +#endif
> +
> + wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
> +
> + /*
> + * Vector to user's handler.
> + *
> + * NOTE: TBR may no longer have vector number in it since
> + * we just enabled traps. It is definitely in l3.
> + */
> +
> + sethi %hi(SYM(_ISR_Vector_table)), %g4
> + or %g4, %lo(SYM(_ISR_Vector_table)), %g4
> + and %l3, 0xFF, %g5 ! remove synchronous trap indicator
> + sll %g5, 2, %g5 ! g5 = offset into table
> + ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
> +
> +
> + ! o1 = 2nd arg = address of the ISF
> + ! WAS LOADED WHEN ISF WAS SAVED!!!
> + mov %l3, %o0 ! o0 = 1st arg = vector number
> + call %g4
> +#if defined(RTEMS_PROFILING)
> + mov %o5, %l3 ! save interrupt entry instant
> +#else
> + nop ! delay slot
> +#endif
> +
> +#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
> + mov %l0, %g1 ! PSR[EF] value of interrupted context
> + ta SPARC_SWTRAP_IRQDIS_FP ! **** DISABLE INTERRUPTS ****
> +#else
> + ta SPARC_SWTRAP_IRQDIS ! **** DISABLE INTERRUPTS ****
> +#endif
> +
> +#if defined(RTEMS_PROFILING)
> + cmp %l7, 0
> + bne profiling_not_outer_most_exit
> + nop
> + call %l4 ! Call _SPARC_Counter.counter_read
> + mov %g1, %l4 ! Save previous interrupt status
> + mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
> + mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
> + call SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
> + mov %g6, %o0 ! o0 = 1st arg = per-CPU control
> +profiling_not_outer_most_exit:
> +#endif
> +
> + /*
> + * Decrement ISR nest level and Thread dispatch disable level.
> + *
> + * Register usage for this section:
> + *
> + * o2 = g6->dispatch_necessary value
> + * o3 = g6->isr_dispatch_disable value
> + * l6 = g6->thread_dispatch_disable_level value
> + * l7 = g6->isr_nest_level value
> + */
> +
> + ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
> + ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
> + st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
> + SPARC_LEON3FT_B2BST_NOP
> + sub %l6, 1, %l6
> + st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
> +
> + /*
> + * Thread dispatching is necessary and allowed if and only if
> + * g6->dispatch_necessary == 1 and
> + * g6->isr_dispatch_disable == 0 and
> + * g6->thread_dispatch_disable_level == 0.
> + *
> + * Otherwise, continue with the simple return.
> + */
> + xor %o2, 1, %o2
> + or %o2, %l6, %o2
> + orcc %o2, %o3, %o2
> + bnz simple_return
> +
> + /*
> + * Switch back on the interrupted tasks stack and add enough room to
> + * invoke the dispatcher. Doing this in the delay slot causes no harm,
> + * since the stack pointer (%sp) is not used in the simple return path.
> + */
> + sub %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
> +
> +isr_dispatch:
> +
> + /* Set ISR dispatch disable and thread dispatch disable level to one */
> + mov 1, %l6
> + st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
> + st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
> +
> + /* Call _Thread_Do_dispatch(), this function will enable interrupts */
> +
> + mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
> +
> +#if defined(SPARC_USE_LAZY_FP_SWITCH)
> + /* Test if we interrupted a floating point thread (PSR[EF] == 1) */
> + andcc %l0, %l5, %g0
> + be .Lnon_fp_thread_dispatch
> + ld [%g6 + PER_CPU_OFFSET_EXECUTING], %l6
> +
> + /* Set new floating point unit owner to executing thread */
> + st %l6, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
> +
> + call SYM(_Thread_Do_dispatch)
> + mov %g6, %o0
> +
> + /*
> + * If we are still the floating point unit owner, then reset the
> + * floating point unit owner to NULL, otherwise clear PSR[EF] in the
> + * interrupt frame and let the FP disabled system call do the floating
> + * point context save/restore.
> + */
> + ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %l7
> + cmp %l6, %l7
> + bne,a .Ldisable_fp
> + andn %l0, %l5, %l0
> + st %g0, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
> + ba .Lthread_dispatch_done
> + nop
> +.Ldisable_fp:
> + st %l0, [%fp + ISF_PSR_OFFSET]
> + ba .Lthread_dispatch_done
> + nop
> +.Lnon_fp_thread_dispatch:
> +#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
> + /* Test if we interrupted a floating point thread (PSR[EF] == 1) */
> + andcc %l0, %l5, %g0
> + be .Lnon_fp_thread_dispatch
> + nop
> +
> + /*
> + * Yes, this is a floating point thread, then save the floating point
> + * context to a new stack frame. Then do the thread dispatch.
> + * Post-switch actions (e.g. signal handlers) and context switch
> + * extensions may safely use the floating point unit.
> + */
> + sub %sp, SPARC_FP_FRAME_SIZE, %sp
> + std %f0, [%sp + SPARC_FP_FRAME_OFFSET_FO_F1]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f2, [%sp + SPARC_FP_FRAME_OFFSET_F2_F3]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f4, [%sp + SPARC_FP_FRAME_OFFSET_F4_F5]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f6, [%sp + SPARC_FP_FRAME_OFFSET_F6_F7]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f8, [%sp + SPARC_FP_FRAME_OFFSET_F8_F9]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f10, [%sp + SPARC_FP_FRAME_OFFSET_F1O_F11]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f12, [%sp + SPARC_FP_FRAME_OFFSET_F12_F13]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f14, [%sp + SPARC_FP_FRAME_OFFSET_F14_F15]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f16, [%sp + SPARC_FP_FRAME_OFFSET_F16_F17]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f18, [%sp + SPARC_FP_FRAME_OFFSET_F18_F19]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f20, [%sp + SPARC_FP_FRAME_OFFSET_F2O_F21]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f22, [%sp + SPARC_FP_FRAME_OFFSET_F22_F23]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f24, [%sp + SPARC_FP_FRAME_OFFSET_F24_F25]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f26, [%sp + SPARC_FP_FRAME_OFFSET_F26_F27]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f28, [%sp + SPARC_FP_FRAME_OFFSET_F28_F29]
> + SPARC_LEON3FT_B2BST_NOP
> + std %f30, [%sp + SPARC_FP_FRAME_OFFSET_F3O_F31]
> + SPARC_LEON3FT_B2BST_NOP
> + st %fsr, [%sp + SPARC_FP_FRAME_OFFSET_FSR]
> + call SYM(_Thread_Do_dispatch)
> + mov %g6, %o0
> +
> + /*
> + * Restore the floating point context from stack frame and release the
> + * stack frame.
> + */
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_FO_F1], %f0
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F2_F3], %f2
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F4_F5], %f4
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F6_F7], %f6
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F8_F9], %f8
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F1O_F11], %f10
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F12_F13], %f12
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F14_F15], %f14
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F16_F17], %f16
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F18_F19], %f18
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F2O_F21], %f20
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F22_F23], %f22
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F24_F25], %f24
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F26_F27], %f26
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F28_F29], %f28
> + ldd [%sp + SPARC_FP_FRAME_OFFSET_F3O_F31], %f30
> + ld [%sp + SPARC_FP_FRAME_OFFSET_FSR], %fsr
> + ba .Lthread_dispatch_done
> + add %sp, SPARC_FP_FRAME_SIZE, %sp
> +
> +.Lnon_fp_thread_dispatch:
> +#endif
> +
> + call SYM(_Thread_Do_dispatch)
> + mov %g6, %o0
> +
> +#if SPARC_HAS_FPU == 1
> +.Lthread_dispatch_done:
> +#endif
> +
> + ta SPARC_SWTRAP_IRQDIS ! **** DISABLE INTERRUPTS ****
> +
> + /*
> + * While we had ISR dispatching disabled in this thread,
> + * did we miss anything? If so, then we need to do another
> + * _Thread_Do_dispatch() before leaving this ISR dispatch context.
> + */
> + ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
> +
> + orcc %l7, %g0, %g0 ! Is a thread dispatch necessary?
> + bne isr_dispatch ! Yes, then invoke the dispatcher again.
> + mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
> +
> + /*
> + * No, then set the ISR dispatch disable flag to zero and continue with
> + * the simple return.
> + */
> + st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
> +
> + /*
> + * The CWP in place at this point may be different from
> + * that which was in effect at the beginning of the ISR if we
> + * have been context switched between the beginning of this invocation
> + * of _ISR_Handler and this point. Thus the CWP and WIM should
> + * not be changed back to their values at ISR entry time. Any
> + * changes to the PSR must preserve the CWP.
> + */
> +
> +simple_return:
> + ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
> + wr %l5, 0, %y
> +
> + ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
> + ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
> + rd %psr, %l3
> + and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
> + andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
> + or %l3, %l0, %l0 ! install it later...
> + andn %l0, SPARC_PSR_ET_MASK, %l0
> +
> + /*
> + * Restore tasks global and out registers
> + */
> +
> + mov %fp, %g1
> +
> + ! g1 is restored later
> + ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
> + ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
> + ld [%fp + ISF_G7_OFFSET], %g7 ! restore g7
> +
> + ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
> + ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
> + ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
> + ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
> +
> + /*
> + * Registers:
> + *
> + * ALL global registers EXCEPT G1 and the input registers have
> + * already been restored and thuse off limits.
> + *
> + * The following is the contents of the local registers:
> + *
> + * l0 = original psr
> + * l1 = return address (i.e. PC)
> + * l2 = nPC
> + * l3 = CWP
> + */
> +
> + /*
> + * if (CWP + 1) is an invalid window then we need to reload it.
> + *
> + * WARNING: Traps should now be disabled
> + */
> +
> + mov %l0, %psr ! **** DISABLE TRAPS ****
> + nop
> + nop
> + nop
> + rd %wim, %l4
> + add %l0, 1, %l6 ! l6 = cwp + 1
> + and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
> + srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
> + ! and CWP are conveniently LS 5 bits
> + cmp %l5, 1 ! Is tasks window invalid?
> + bne good_task_window
> +
> + /*
> + * The following code is the same as a 1 position left rotate of WIM.
> + */
> +
> + sll %l4, 1, %l5 ! l5 = WIM << 1
> + srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
> + ! l4 = WIM >> (Number Windows - 1)
> + or %l4, %l5, %l4 ! l4 = (WIM << 1) |
> + ! (WIM >> (Number Windows - 1))
> +
> + /*
> + * Now restore the window just as if we underflowed to it.
> + */
> +
> + wr %l4, 0, %wim ! WIM = new WIM
> + nop ! must delay after writing WIM
> + nop
> + nop
> + restore ! now into the tasks window
> +
> + ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
> + ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
> + ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
> + ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
> + ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
> + ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
> + ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
> + ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
> + ! reload of sp clobbers ISF
> + save ! Back to ISR dispatch window
> +
> +good_task_window:
> + TN0018_WAIT_IFLUSH %l3,%l4 ! GRLIB-TN-0018 work around macro
> +
> + mov %l0, %psr ! **** DISABLE TRAPS ****
> + nop; nop; nop
> + ! and restore condition codes.
> + ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
> + TN0018_FIX %l3,%l4 ! GRLIB-TN-0018 work around macro
> + jmp %l1 ! transfer control and
> + rett %l2 ! go back to tasks window
> +
> +/* end of file */
> diff --git a/spec/build/cpukit/cpusparc.yml b/spec/build/cpukit/cpusparc.yml
> index 2186505577..5cd6cd7998 100644
> --- a/spec/build/cpukit/cpusparc.yml
> +++ b/spec/build/cpukit/cpusparc.yml
> @@ -39,6 +39,7 @@ source:
> - cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
> - cpukit/score/cpu/sparc/sparc-counter-asm.S
> - cpukit/score/cpu/sparc/sparc-exception-frame-print.c
> +- cpukit/score/cpu/sparc/sparc-isr-handler.S
> - cpukit/score/cpu/sparc/sparc-isr-install.c
> - cpukit/score/cpu/sparc/syscall.S
> - cpukit/score/cpu/sparc/window.S
> --
> 2.26.2
>
>
>
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