[PATCH v1 3/8] cpukit/aarch64: Use correct debug register names
Kinsey Moore
kinsey.moore at oarcorp.com
Fri Oct 29 21:17:16 UTC 2021
The N used in the breakpoint and watchpoint register names is intended
to be an integer between 0 and 15 (inclusive) and will not compile when
used as is. This adds the accessors necessary to access all of these
breakpoint and watchpoint registers.
---
.../rtems/score/aarch64-system-registers.h | 1364 +++++++++++++++--
1 file changed, 1222 insertions(+), 142 deletions(-)
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
index dc2afdeca8..5bfddb6dad 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
@@ -6719,21 +6719,291 @@ static inline uint64_t _AArch64_Read_dbgauthstatus_el1( void )
#define AARCH64_DBGBCR_N_EL1_BT_GET( _reg ) \
( ( ( _reg ) >> 20 ) & 0xfU )
-static inline uint64_t _AArch64_Read_dbgbcr_n_el1( void )
+static inline uint64_t _AArch64_Read_dbgbcr0_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGBCR_N_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGBCR0_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgbcr_n_el1( uint64_t value )
+static inline void _AArch64_Write_dbgbcr0_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGBCR_N_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGBCR0_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr1_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR1_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr1_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR1_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr2_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR2_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr2_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR2_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr3_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR3_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr3_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR3_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr4_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR4_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr4_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR4_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr5_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR5_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr5_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR5_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr6_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR6_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr6_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR6_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr7_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR7_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr7_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR7_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr8_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR8_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr8_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR8_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr9_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR9_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr9_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR9_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr10_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR10_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr10_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR10_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr11_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR11_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr11_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR11_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr12_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR12_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr12_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR12_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr13_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR13_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr13_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR13_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr14_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR14_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr14_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR14_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbcr15_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBCR15_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbcr15_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBCR15_EL1, %0" : : "r" ( value ) : "memory"
);
}
@@ -6781,305 +7051,1115 @@ static inline void _AArch64_Write_dbgbcr_n_el1( uint64_t value )
#define AARCH64_DBGBVR_N_EL1_RESS_14_4_GET( _reg ) \
( ( ( _reg ) >> 53 ) & 0x7ffULL )
-static inline uint64_t _AArch64_Read_dbgbvr_n_el1( void )
+static inline uint64_t _AArch64_Read_dbgbvr0_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR0_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr0_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR0_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr1_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR1_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr1_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR1_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr2_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR2_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr2_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR2_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr3_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR3_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr3_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR3_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr4_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR4_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr4_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR4_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr5_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR5_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr5_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR5_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr6_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR6_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr6_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR6_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr7_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR7_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr7_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR7_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr8_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR8_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr8_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR8_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr9_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR9_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr9_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR9_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr10_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR10_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr10_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR10_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr11_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR11_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr11_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR11_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr12_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR12_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr12_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR12_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr13_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR13_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr13_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR13_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr14_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR14_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr14_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR14_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgbvr15_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGBVR15_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgbvr15_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGBVR15_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register */
+
+#define AARCH64_DBGCLAIMCLR_EL1_CLAIM( _val ) ( ( _val ) << 0 )
+#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_SHIFT 0
+#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_MASK 0xffU
+#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_GET( _reg ) \
+ ( ( ( _reg ) >> 0 ) & 0xffU )
+
+static inline uint64_t _AArch64_Read_dbgclaimclr_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGCLAIMCLR_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgclaimclr_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGCLAIMCLR_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register */
+
+#define AARCH64_DBGCLAIMSET_EL1_CLAIM( _val ) ( ( _val ) << 0 )
+#define AARCH64_DBGCLAIMSET_EL1_CLAIM_SHIFT 0
+#define AARCH64_DBGCLAIMSET_EL1_CLAIM_MASK 0xffU
+#define AARCH64_DBGCLAIMSET_EL1_CLAIM_GET( _reg ) \
+ ( ( ( _reg ) >> 0 ) & 0xffU )
+
+static inline uint64_t _AArch64_Read_dbgclaimset_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGCLAIMSET_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgclaimset_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGCLAIMSET_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGDTR_EL0, Debug Data Transfer Register, half-duplex */
+
+#define AARCH64_DBGDTR_EL0_LOWWORD( _val ) ( ( _val ) << 0 )
+#define AARCH64_DBGDTR_EL0_LOWWORD_SHIFT 0
+#define AARCH64_DBGDTR_EL0_LOWWORD_MASK 0xffffffffU
+#define AARCH64_DBGDTR_EL0_LOWWORD_GET( _reg ) \
+ ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+
+#define AARCH64_DBGDTR_EL0_HIGHWORD( _val ) ( ( _val ) << 32 )
+#define AARCH64_DBGDTR_EL0_HIGHWORD_SHIFT 32
+#define AARCH64_DBGDTR_EL0_HIGHWORD_MASK 0xffffffff00000000ULL
+#define AARCH64_DBGDTR_EL0_HIGHWORD_GET( _reg ) \
+ ( ( ( _reg ) >> 32 ) & 0xffffffffULL )
+
+static inline uint64_t _AArch64_Read_dbgdtr_el0( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGDTR_EL0" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgdtr_el0( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGDTR_EL0, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGDTRRX_EL0, Debug Data Transfer Register, Receive */
+
+static inline uint64_t _AArch64_Read_dbgdtrrx_el0( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGDTRRX_EL0" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+/* DBGDTRTX_EL0, Debug Data Transfer Register, Transmit */
+
+static inline void _AArch64_Write_dbgdtrtx_el0( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGDTRTX_EL0, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGPRCR_EL1, Debug Power Control Register */
+
+#define AARCH64_DBGPRCR_EL1_CORENPDRQ 0x1U
+
+static inline uint64_t _AArch64_Read_dbgprcr_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGPRCR_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgprcr_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGPRCR_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGVCR32_EL2, Debug Vector Catch Register */
+
+#define AARCH64_DBGVCR32_EL2_SU 0x2U
+
+#define AARCH64_DBGVCR32_EL2_U 0x2U
+
+#define AARCH64_DBGVCR32_EL2_S 0x4U
+
+#define AARCH64_DBGVCR32_EL2_SS 0x4U
+
+#define AARCH64_DBGVCR32_EL2_P 0x8U
+
+#define AARCH64_DBGVCR32_EL2_SP 0x8U
+
+#define AARCH64_DBGVCR32_EL2_D 0x10U
+
+#define AARCH64_DBGVCR32_EL2_SD 0x10U
+
+#define AARCH64_DBGVCR32_EL2_I 0x40U
+
+#define AARCH64_DBGVCR32_EL2_SI 0x40U
+
+#define AARCH64_DBGVCR32_EL2_F 0x80U
+
+#define AARCH64_DBGVCR32_EL2_SF 0x80U
+
+#define AARCH64_DBGVCR32_EL2_NSU 0x2000000U
+
+#define AARCH64_DBGVCR32_EL2_NSS 0x4000000U
+
+#define AARCH64_DBGVCR32_EL2_NSP 0x8000000U
+
+#define AARCH64_DBGVCR32_EL2_NSD 0x10000000U
+
+#define AARCH64_DBGVCR32_EL2_NSI 0x40000000U
+
+#define AARCH64_DBGVCR32_EL2_NSF 0x80000000U
+
+static inline uint64_t _AArch64_Read_dbgvcr32_el2( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGVCR32_EL2" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgvcr32_el2( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGVCR32_EL2, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+/* DBGWCR_N_EL1, Debug Watchpoint Control Registers, n = 0 - 15 */
+
+#define AARCH64_DBGWCR_N_EL1_E 0x1U
+
+#define AARCH64_DBGWCR_N_EL1_PAC( _val ) ( ( _val ) << 1 )
+#define AARCH64_DBGWCR_N_EL1_PAC_SHIFT 1
+#define AARCH64_DBGWCR_N_EL1_PAC_MASK 0x6U
+#define AARCH64_DBGWCR_N_EL1_PAC_GET( _reg ) \
+ ( ( ( _reg ) >> 1 ) & 0x3U )
+
+#define AARCH64_DBGWCR_N_EL1_LSC( _val ) ( ( _val ) << 3 )
+#define AARCH64_DBGWCR_N_EL1_LSC_SHIFT 3
+#define AARCH64_DBGWCR_N_EL1_LSC_MASK 0x18U
+#define AARCH64_DBGWCR_N_EL1_LSC_GET( _reg ) \
+ ( ( ( _reg ) >> 3 ) & 0x3U )
+
+#define AARCH64_DBGWCR_N_EL1_BAS( _val ) ( ( _val ) << 5 )
+#define AARCH64_DBGWCR_N_EL1_BAS_SHIFT 5
+#define AARCH64_DBGWCR_N_EL1_BAS_MASK 0x1fe0U
+#define AARCH64_DBGWCR_N_EL1_BAS_GET( _reg ) \
+ ( ( ( _reg ) >> 5 ) & 0xffU )
+
+#define AARCH64_DBGWCR_N_EL1_HMC 0x2000U
+
+#define AARCH64_DBGWCR_N_EL1_SSC( _val ) ( ( _val ) << 14 )
+#define AARCH64_DBGWCR_N_EL1_SSC_SHIFT 14
+#define AARCH64_DBGWCR_N_EL1_SSC_MASK 0xc000U
+#define AARCH64_DBGWCR_N_EL1_SSC_GET( _reg ) \
+ ( ( ( _reg ) >> 14 ) & 0x3U )
+
+#define AARCH64_DBGWCR_N_EL1_LBN( _val ) ( ( _val ) << 16 )
+#define AARCH64_DBGWCR_N_EL1_LBN_SHIFT 16
+#define AARCH64_DBGWCR_N_EL1_LBN_MASK 0xf0000U
+#define AARCH64_DBGWCR_N_EL1_LBN_GET( _reg ) \
+ ( ( ( _reg ) >> 16 ) & 0xfU )
+
+#define AARCH64_DBGWCR_N_EL1_WT 0x100000U
+
+#define AARCH64_DBGWCR_N_EL1_MASK( _val ) ( ( _val ) << 24 )
+#define AARCH64_DBGWCR_N_EL1_MASK_SHIFT 24
+#define AARCH64_DBGWCR_N_EL1_MASK_MASK 0x1f000000U
+#define AARCH64_DBGWCR_N_EL1_MASK_GET( _reg ) \
+ ( ( ( _reg ) >> 24 ) & 0x1fU )
+
+static inline uint64_t _AArch64_Read_dbgwcr0_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR0_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr0_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR0_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr1_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR1_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr1_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR1_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr2_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR2_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr2_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR2_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr3_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR3_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr3_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR3_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr4_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR4_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr4_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR4_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr5_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR5_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr5_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR5_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr6_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR6_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr6_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR6_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr7_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR7_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr7_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR7_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr8_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR8_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr8_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR8_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr9_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR9_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr9_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR9_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr10_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR10_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr10_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR10_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr11_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR11_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr11_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR11_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr12_el1( void )
+{
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, DBGWCR12_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwcr12_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWCR12_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwcr13_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGBVR_N_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWCR13_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgbvr_n_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwcr13_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGBVR_N_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWCR13_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register */
-
-#define AARCH64_DBGCLAIMCLR_EL1_CLAIM( _val ) ( ( _val ) << 0 )
-#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_SHIFT 0
-#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_MASK 0xffU
-#define AARCH64_DBGCLAIMCLR_EL1_CLAIM_GET( _reg ) \
- ( ( ( _reg ) >> 0 ) & 0xffU )
-
-static inline uint64_t _AArch64_Read_dbgclaimclr_el1( void )
+static inline uint64_t _AArch64_Read_dbgwcr14_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGCLAIMCLR_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWCR14_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgclaimclr_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwcr14_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGCLAIMCLR_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWCR14_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register */
-
-#define AARCH64_DBGCLAIMSET_EL1_CLAIM( _val ) ( ( _val ) << 0 )
-#define AARCH64_DBGCLAIMSET_EL1_CLAIM_SHIFT 0
-#define AARCH64_DBGCLAIMSET_EL1_CLAIM_MASK 0xffU
-#define AARCH64_DBGCLAIMSET_EL1_CLAIM_GET( _reg ) \
- ( ( ( _reg ) >> 0 ) & 0xffU )
-
-static inline uint64_t _AArch64_Read_dbgclaimset_el1( void )
+static inline uint64_t _AArch64_Read_dbgwcr15_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGCLAIMSET_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWCR15_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgclaimset_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwcr15_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGCLAIMSET_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWCR15_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGDTR_EL0, Debug Data Transfer Register, half-duplex */
+/* DBGWVR_N_EL1, Debug Watchpoint Value Registers, n = 0 - 15 */
-#define AARCH64_DBGDTR_EL0_LOWWORD( _val ) ( ( _val ) << 0 )
-#define AARCH64_DBGDTR_EL0_LOWWORD_SHIFT 0
-#define AARCH64_DBGDTR_EL0_LOWWORD_MASK 0xffffffffU
-#define AARCH64_DBGDTR_EL0_LOWWORD_GET( _reg ) \
- ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define AARCH64_DBGWVR_N_EL1_VA_48_2( _val ) ( ( _val ) << 2 )
+#define AARCH64_DBGWVR_N_EL1_VA_48_2_SHIFT 2
+#define AARCH64_DBGWVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL
+#define AARCH64_DBGWVR_N_EL1_VA_48_2_GET( _reg ) \
+ ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL )
-#define AARCH64_DBGDTR_EL0_HIGHWORD( _val ) ( ( _val ) << 32 )
-#define AARCH64_DBGDTR_EL0_HIGHWORD_SHIFT 32
-#define AARCH64_DBGDTR_EL0_HIGHWORD_MASK 0xffffffff00000000ULL
-#define AARCH64_DBGDTR_EL0_HIGHWORD_GET( _reg ) \
- ( ( ( _reg ) >> 32 ) & 0xffffffffULL )
+#define AARCH64_DBGWVR_N_EL1_VA_52_49( _val ) ( ( _val ) << 49 )
+#define AARCH64_DBGWVR_N_EL1_VA_52_49_SHIFT 49
+#define AARCH64_DBGWVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL
+#define AARCH64_DBGWVR_N_EL1_VA_52_49_GET( _reg ) \
+ ( ( ( _reg ) >> 49 ) & 0xfULL )
-static inline uint64_t _AArch64_Read_dbgdtr_el0( void )
+#define AARCH64_DBGWVR_N_EL1_RESS_14_4( _val ) ( ( _val ) << 53 )
+#define AARCH64_DBGWVR_N_EL1_RESS_14_4_SHIFT 53
+#define AARCH64_DBGWVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL
+#define AARCH64_DBGWVR_N_EL1_RESS_14_4_GET( _reg ) \
+ ( ( ( _reg ) >> 53 ) & 0x7ffULL )
+
+static inline uint64_t _AArch64_Read_dbgwvr0_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGDTR_EL0" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR0_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgdtr_el0( uint64_t value )
+static inline void _AArch64_Write_dbgwvr0_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGDTR_EL0, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR0_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGDTRRX_EL0, Debug Data Transfer Register, Receive */
-
-static inline uint64_t _AArch64_Read_dbgdtrrx_el0( void )
+static inline uint64_t _AArch64_Read_dbgwvr1_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGDTRRX_EL0" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR1_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-/* DBGDTRTX_EL0, Debug Data Transfer Register, Transmit */
-
-static inline void _AArch64_Write_dbgdtrtx_el0( uint64_t value )
+static inline void _AArch64_Write_dbgwvr1_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGDTRTX_EL0, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR1_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGPRCR_EL1, Debug Power Control Register */
+static inline uint64_t _AArch64_Read_dbgwvr2_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGPRCR_EL1_CORENPDRQ 0x1U
+ __asm__ volatile (
+ "mrs %0, DBGWVR2_EL1" : "=&r" ( value ) : : "memory"
+ );
-static inline uint64_t _AArch64_Read_dbgprcr_el1( void )
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwvr2_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR2_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwvr3_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGPRCR_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR3_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgprcr_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwvr3_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGPRCR_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR3_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGVCR32_EL2, Debug Vector Catch Register */
+static inline uint64_t _AArch64_Read_dbgwvr4_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGVCR32_EL2_SU 0x2U
+ __asm__ volatile (
+ "mrs %0, DBGWVR4_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGVCR32_EL2_U 0x2U
+ return value;
+}
-#define AARCH64_DBGVCR32_EL2_S 0x4U
+static inline void _AArch64_Write_dbgwvr4_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR4_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGVCR32_EL2_SS 0x4U
+static inline uint64_t _AArch64_Read_dbgwvr5_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGVCR32_EL2_P 0x8U
+ __asm__ volatile (
+ "mrs %0, DBGWVR5_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGVCR32_EL2_SP 0x8U
+ return value;
+}
-#define AARCH64_DBGVCR32_EL2_D 0x10U
+static inline void _AArch64_Write_dbgwvr5_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR5_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGVCR32_EL2_SD 0x10U
+static inline uint64_t _AArch64_Read_dbgwvr6_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGVCR32_EL2_I 0x40U
+ __asm__ volatile (
+ "mrs %0, DBGWVR6_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGVCR32_EL2_SI 0x40U
+ return value;
+}
-#define AARCH64_DBGVCR32_EL2_F 0x80U
+static inline void _AArch64_Write_dbgwvr6_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR6_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGVCR32_EL2_SF 0x80U
+static inline uint64_t _AArch64_Read_dbgwvr7_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGVCR32_EL2_NSU 0x2000000U
+ __asm__ volatile (
+ "mrs %0, DBGWVR7_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGVCR32_EL2_NSS 0x4000000U
+ return value;
+}
-#define AARCH64_DBGVCR32_EL2_NSP 0x8000000U
+static inline void _AArch64_Write_dbgwvr7_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR7_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGVCR32_EL2_NSD 0x10000000U
+static inline uint64_t _AArch64_Read_dbgwvr8_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGVCR32_EL2_NSI 0x40000000U
+ __asm__ volatile (
+ "mrs %0, DBGWVR8_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGVCR32_EL2_NSF 0x80000000U
+ return value;
+}
-static inline uint64_t _AArch64_Read_dbgvcr32_el2( void )
+static inline void _AArch64_Write_dbgwvr8_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR8_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
+
+static inline uint64_t _AArch64_Read_dbgwvr9_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGVCR32_EL2" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR9_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgvcr32_el2( uint64_t value )
+static inline void _AArch64_Write_dbgwvr9_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGVCR32_EL2, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR9_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGWCR_N_EL1, Debug Watchpoint Control Registers, n = 0 - 15 */
+static inline uint64_t _AArch64_Read_dbgwvr10_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGWCR_N_EL1_E 0x1U
+ __asm__ volatile (
+ "mrs %0, DBGWVR10_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGWCR_N_EL1_PAC( _val ) ( ( _val ) << 1 )
-#define AARCH64_DBGWCR_N_EL1_PAC_SHIFT 1
-#define AARCH64_DBGWCR_N_EL1_PAC_MASK 0x6U
-#define AARCH64_DBGWCR_N_EL1_PAC_GET( _reg ) \
- ( ( ( _reg ) >> 1 ) & 0x3U )
+ return value;
+}
-#define AARCH64_DBGWCR_N_EL1_LSC( _val ) ( ( _val ) << 3 )
-#define AARCH64_DBGWCR_N_EL1_LSC_SHIFT 3
-#define AARCH64_DBGWCR_N_EL1_LSC_MASK 0x18U
-#define AARCH64_DBGWCR_N_EL1_LSC_GET( _reg ) \
- ( ( ( _reg ) >> 3 ) & 0x3U )
+static inline void _AArch64_Write_dbgwvr10_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR10_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGWCR_N_EL1_BAS( _val ) ( ( _val ) << 5 )
-#define AARCH64_DBGWCR_N_EL1_BAS_SHIFT 5
-#define AARCH64_DBGWCR_N_EL1_BAS_MASK 0x1fe0U
-#define AARCH64_DBGWCR_N_EL1_BAS_GET( _reg ) \
- ( ( ( _reg ) >> 5 ) & 0xffU )
+static inline uint64_t _AArch64_Read_dbgwvr11_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGWCR_N_EL1_HMC 0x2000U
+ __asm__ volatile (
+ "mrs %0, DBGWVR11_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGWCR_N_EL1_SSC( _val ) ( ( _val ) << 14 )
-#define AARCH64_DBGWCR_N_EL1_SSC_SHIFT 14
-#define AARCH64_DBGWCR_N_EL1_SSC_MASK 0xc000U
-#define AARCH64_DBGWCR_N_EL1_SSC_GET( _reg ) \
- ( ( ( _reg ) >> 14 ) & 0x3U )
+ return value;
+}
-#define AARCH64_DBGWCR_N_EL1_LBN( _val ) ( ( _val ) << 16 )
-#define AARCH64_DBGWCR_N_EL1_LBN_SHIFT 16
-#define AARCH64_DBGWCR_N_EL1_LBN_MASK 0xf0000U
-#define AARCH64_DBGWCR_N_EL1_LBN_GET( _reg ) \
- ( ( ( _reg ) >> 16 ) & 0xfU )
+static inline void _AArch64_Write_dbgwvr11_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR11_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-#define AARCH64_DBGWCR_N_EL1_WT 0x100000U
+static inline uint64_t _AArch64_Read_dbgwvr12_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGWCR_N_EL1_MASK( _val ) ( ( _val ) << 24 )
-#define AARCH64_DBGWCR_N_EL1_MASK_SHIFT 24
-#define AARCH64_DBGWCR_N_EL1_MASK_MASK 0x1f000000U
-#define AARCH64_DBGWCR_N_EL1_MASK_GET( _reg ) \
- ( ( ( _reg ) >> 24 ) & 0x1fU )
+ __asm__ volatile (
+ "mrs %0, DBGWVR12_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ return value;
+}
+
+static inline void _AArch64_Write_dbgwvr12_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR12_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-static inline uint64_t _AArch64_Read_dbgwcr_n_el1( void )
+static inline uint64_t _AArch64_Read_dbgwvr13_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGWCR_N_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR13_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgwcr_n_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwvr13_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGWCR_N_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR13_EL1, %0" : : "r" ( value ) : "memory"
);
}
-/* DBGWVR_N_EL1, Debug Watchpoint Value Registers, n = 0 - 15 */
+static inline uint64_t _AArch64_Read_dbgwvr14_el1( void )
+{
+ uint64_t value;
-#define AARCH64_DBGWVR_N_EL1_VA_48_2( _val ) ( ( _val ) << 2 )
-#define AARCH64_DBGWVR_N_EL1_VA_48_2_SHIFT 2
-#define AARCH64_DBGWVR_N_EL1_VA_48_2_MASK 0x1fffffffffffcULL
-#define AARCH64_DBGWVR_N_EL1_VA_48_2_GET( _reg ) \
- ( ( ( _reg ) >> 2 ) & 0x7fffffffffffULL )
+ __asm__ volatile (
+ "mrs %0, DBGWVR14_EL1" : "=&r" ( value ) : : "memory"
+ );
-#define AARCH64_DBGWVR_N_EL1_VA_52_49( _val ) ( ( _val ) << 49 )
-#define AARCH64_DBGWVR_N_EL1_VA_52_49_SHIFT 49
-#define AARCH64_DBGWVR_N_EL1_VA_52_49_MASK 0x1e000000000000ULL
-#define AARCH64_DBGWVR_N_EL1_VA_52_49_GET( _reg ) \
- ( ( ( _reg ) >> 49 ) & 0xfULL )
+ return value;
+}
-#define AARCH64_DBGWVR_N_EL1_RESS_14_4( _val ) ( ( _val ) << 53 )
-#define AARCH64_DBGWVR_N_EL1_RESS_14_4_SHIFT 53
-#define AARCH64_DBGWVR_N_EL1_RESS_14_4_MASK 0xffe0000000000000ULL
-#define AARCH64_DBGWVR_N_EL1_RESS_14_4_GET( _reg ) \
- ( ( ( _reg ) >> 53 ) & 0x7ffULL )
+static inline void _AArch64_Write_dbgwvr14_el1( uint64_t value )
+{
+ __asm__ volatile (
+ "msr DBGWVR14_EL1, %0" : : "r" ( value ) : "memory"
+ );
+}
-static inline uint64_t _AArch64_Read_dbgwvr_n_el1( void )
+static inline uint64_t _AArch64_Read_dbgwvr15_el1( void )
{
uint64_t value;
__asm__ volatile (
- "mrs %0, DBGWVR_N_EL1" : "=&r" ( value ) : : "memory"
+ "mrs %0, DBGWVR15_EL1" : "=&r" ( value ) : : "memory"
);
return value;
}
-static inline void _AArch64_Write_dbgwvr_n_el1( uint64_t value )
+static inline void _AArch64_Write_dbgwvr15_el1( uint64_t value )
{
__asm__ volatile (
- "msr DBGWVR_N_EL1, %0" : : "r" ( value ) : "memory"
+ "msr DBGWVR15_EL1, %0" : : "r" ( value ) : "memory"
);
}
--
2.30.2
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