[PATCH 3/3] aarch64/gicv3: Remove accesses to secure registers

[Gedare Bloom]

On Mon, Jun 13, 2022 at 7:39 PM <chrisj at rtems.org> wrote:
>
> From: Chris Johns <chrisj at rtems.org>
>
> ---
>  bsps/include/dev/irq/arm-gicv3.h | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
> index 0d3ef9a1c1..a79368ebdf 100644
> --- a/bsps/include/dev/irq/arm-gicv3.h
> +++ b/bsps/include/dev/irq/arm-gicv3.h
> @@ -300,12 +300,25 @@ static void gicv3_init_dist(volatile gic_dist *dist)
>    }
>  }
>
> +/*
> + * A better way to access these registers than special opcodes
> + */
> +#define isb() __asm __volatile("isb" : : : "memory")
> +
> +#define  WRITE_SPECIALREG(reg, _val)                                    \
> +  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
> +
> +#define  gic_icc_write(reg, val)            \
> +do {                                        \
> +  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
> +  isb();                                    \
> +} while (0)
> +
>  static void gicv3_init_cpu_interface(uint32_t cpu_index)
>  {
>    uint32_t sre_value = 0x7;
>    WRITE_SR(ICC_SRE, sre_value);
>    WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
> -  WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));
This appears unrelated?

>
>    volatile gic_redist *redist = gicv3_get_redist(cpu_index);
>    uint32_t waker = redist->icrwaker;
> @@ -322,8 +335,7 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
>    }
>
>    /* Enable interrupt groups 0 and 1 */
> -  WRITE_SR(ICC_IGRPEN0, 0x1);
> -  WRITE_SR(ICC_IGRPEN1, 0x1);
> +  gic_icc_write(IGRPEN1, 1);
Removed the write to IGRPEN0?

>    WRITE_SR(ICC_CTLR, 0x0);
>  }
>
> --
> 2.19.1
>
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