[PATCH] arm/gicv3: Fix building arm/r52

Chris Johns chrisj at rtems.org
Mon Jun 27 03:02:46 UTC 2022


On 24/6/2022 7:44 pm, Sebastian Huber wrote:
> On 20.06.22 04:03, chrisj at rtems.org wrote:
>> From: Chris Johns <chrisj at rtems.org>
>>
>> ---
>>   bsps/include/dev/irq/arm-gicv3.h | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
>> index a79368ebdf..aac02fa191 100644
>> --- a/bsps/include/dev/irq/arm-gicv3.h
>> +++ b/bsps/include/dev/irq/arm-gicv3.h
>> @@ -335,7 +335,12 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
>>     }
>>       /* Enable interrupt groups 0 and 1 */
>> +#ifdef ARM_MULTILIB_ARCH_V4
>> +  WRITE_SR(ICC_IGRPEN0, 0x1);
>> +  WRITE_SR(ICC_IGRPEN1, 0x1);
>> +#else
>>     gic_icc_write(IGRPEN1, 1);
>> +#endif
>>     WRITE_SR(ICC_CTLR, 0x0);
>>   }
> 
> I have a different patch to fix this:
> 
> https://lists.rtems.org/pipermail/devel/2022-June/072056.html

Does this change work on a real aarch64 with a suitably configured TF-A? The
security profile of the TF-A needs to disable EL1 access to these registers to
see the issue.

> Why was the isb added?

https://github.com/freebsd/freebsd-src/blob/main/sys/arm64/arm64/gic_v3_reg.h#L458

Sorry I have no idea what specific role it plays. I just copied what they had
and it worked.

> Why was the IGRPEN0 write removed in
> e70384d3f406251422bac64d11ff44570a678434?

Because it generates an exception to EL3 and a write does not work on aarch64
hardware with a TF-A that secures this register.

A review of Linux and FreeBSD showed no access to this register and my brief and
incomplete reading of the GICv3 showed they are related secure interrupts. It
therefore makes sense they are secured and not accessible. Secure modes are the
domain of EL3 code and not EL1.

Please do not remove those calls.

> I have to check if the removed ICC_BPR0 is an issue for AArch32.

The variants do make this more complex. That arch may require a suitably
configured vertical stack like the FPD scalar cores on the Versal does.

Chris


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