[PATCH] bsps/riscv: Clear interrupt complete before disable

Sebastian Huber sebastian.huber at embedded-brains.de
Mon Mar 6 07:01:24 UTC 2023

Hello Padmarao,

On 03.03.23 15:55, Padmarao.Begari at microchip.com wrote:
>> On Thu, 2023-03-02 at 15:18 +0100, Sebastian Huber wrote:
>> On 27.02.23 16:51, Padmarao Begari wrote:
>>> The interrupt complete should clear with the interrupt
>>> number before disabling the interrupt in the PLIC to
>>> get the next interrupt.
>> Which problem does this patch address?
> The problem occurs when the interrupt register(enabled) in the RTEMS-
> LIBBSD drivers and want to serve the interrupt subroutine in the RTEMS.
> Example : CGEM driver
> When the application running to test the CGEM driver with RTEMS +
> RTEMS-LIBBSD, The interrupt is occurred while transmiting the ethernet
> pocket, the RTEMS is received the interrupt but not served with the
> register interrupt subroutine instead it disable the interrupt and set
> the "RTEMS_EVENT_SYSTEM_SERVER", while completing the ISR it is
> clearing the interrupt complete register but there is no effect and the
> next transmit pocket intereupt is not occurred because the interrupt is
> disabled before the interrupt complete clear.
> RISC-V interrupt stacktrace
> **************************
> _RISCV_Exception_handler()
> _RISCV_Interrupt_dispatch()
> bsp_interrupt_handler_dispatch_unchecked()
> bsp_interrupt_dispatch_entries()
>   ( *entry->handler )( entry->arg ); -> bsp_interrupt_server_trigger()
> bsp_interrupt_server_trigger()
> bsp_interrupt_is_valid_vector()
> bsp_interrupt_vector_disable()
> rtems_event_system_send()
> *************************

The claim complete register is written after the interrupt handler dispatch:

     while ((interrupt_index = plic_hart_regs->claim_complete) != 0) {

       plic_hart_regs->claim_complete = interrupt_index;

If you write to the claim complete register also in the interrupt 
disable function, then this write is done twice.

The interrupt disable function may be used in other contexts as well so 
doing a write to the claim complete register may have unexpected side 

We should first figure out why the current implementation which works 
with several other interrupt controllers doesn't work with the PLIC. Is 
the claim complete message ignored if the interrupt is disabled?

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