[PATCH] bsps/riscv: Clear interrupt complete before disable
Sebastian Huber
sebastian.huber at embedded-brains.de
Mon Mar 6 10:19:05 UTC 2023
On 06.03.23 10:24, Padmarao.Begari at microchip.com wrote:
> Hi Sebastian,
>
>> On Mon, 2023-03-06 at 09:41 +0100, Sebastian Huber wrote:
>>
>> On 06.03.23 09:37, Padmarao.Begari at microchip.com wrote:
>>>> Is
>>>> the claim complete message ignored if the interrupt is disabled?
>>>>
>>> Yes.
>>
>> Is this an intended and documented behaviour of the PLIC?
>
> Not documented
Is this a common PLIC behaviour or just the case for the MicroChip
implementation?
>> This is a
>> hardware bug from my point of view. If we really need a software
>> workround just for the PLIC to work with the interrupt server, then
>> we
>> should add a new function for this and keep the interrupt disable as
>> is.
>
> Ok
You could for example add a bsp_interrupt_vector_server_disable() which
defaults to bsp_interrupt_vector_disable().
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