[PATCH 2/2] bsps/riscv: add riscv/kendrytek210 BSP variant
Alan Cudmore
alan.cudmore at gmail.com
Fri Mar 10 03:48:27 UTC 2023
This patch set adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses existing PLIC, Timer, and console UART. It only needs
SoC specific initalization and an embedded device tree binary similar
to the polarfire SoC BSP.
Updates #4876
---
bsps/riscv/riscv/config/kendrytek210.cfg | 9 +
bsps/riscv/riscv/console/console-config.c | 10 +-
bsps/riscv/riscv/console/fe310-uart.c | 2 +-
bsps/riscv/riscv/dts/kendryte-k210.dts | 216 ++++++++++++
bsps/riscv/riscv/include/bsp.h | 4 +
bsps/riscv/riscv/include/bsp/k210.h | 91 +++++
.../riscv/include/bsp/kendryte-k210-dtb.h | 315 ++++++++++++++++++
bsps/riscv/riscv/include/bsp/riscv.h | 4 +
bsps/riscv/riscv/start/bspstart.c | 42 +++
9 files changed, 687 insertions(+), 6 deletions(-)
create mode 100644 bsps/riscv/riscv/config/kendrytek210.cfg
create mode 100644 bsps/riscv/riscv/dts/kendryte-k210.dts
create mode 100644 bsps/riscv/riscv/include/bsp/k210.h
create mode 100644 bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h
diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg b/bsps/riscv/riscv/config/kendrytek210.cfg
new file mode 100644
index 0000000000..b04e78b0e9
--- /dev/null
+++ b/bsps/riscv/riscv/config/kendrytek210.cfg
@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c
index 4916191e0b..72743fe9d5 100644
--- a/bsps/riscv/riscv/console/console-config.c
+++ b/bsps/riscv/riscv/console/console-config.c
@@ -55,7 +55,7 @@
#include <libfdt.h>
#include <string.h>
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
#include <bsp/fe310-uart.h>
static fe310_uart_context fe310_uart_instance;
#endif
@@ -239,7 +239,7 @@ static void riscv_console_probe(void)
}
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {
fe310_uart_context *ctx;
@@ -255,7 +255,7 @@ static void riscv_console_probe(void)
riscv_console.getchar = fe310_uart_read;
}
- rtems_termios_device_context_initialize(&ctx->base, "FE310UART");
+ rtems_termios_device_context_initialize(&ctx->base, "SIFIVEUART");
}
#endif
@@ -290,7 +290,7 @@ rtems_status_code console_initialize(
size_t i;
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
fe310_uart_context *ctx;
char fe310_path[] = "/dev/ttyS0";
#endif
@@ -326,7 +326,7 @@ rtems_status_code console_initialize(
}
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
ctx = &fe310_uart_instance;
rtems_termios_device_install(
fe310_path,
diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c
index 506521add0..ddabcff4c8 100644
--- a/bsps/riscv/riscv/console/fe310-uart.c
+++ b/bsps/riscv/riscv/console/fe310-uart.c
@@ -53,7 +53,7 @@ static void fe310_uart_write (
fe310_uart_context * ctx = (fe310_uart_context*) base;
size_t i;
- ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;
+ ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF;
ctx->regs->txctrl |= 1;
ctx->regs->rxctrl |= 1;
diff --git a/bsps/riscv/riscv/dts/kendryte-k210.dts b/bsps/riscv/riscv/dts/kendryte-k210.dts
new file mode 100644
index 0000000000..379aaf01a3
--- /dev/null
+++ b/bsps/riscv/riscv/dts/kendryte-k210.dts
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) Alan Cudmore
+ * Copyright (C) Padmarao Begari
+ * Copyright (C) 2022 Microchip Technology Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /* This is a device tree for the Kendryte K210 SoC. It is a simplified tree
+ * to support the current RTEMS BSP, but it is not sufficient enough for
+ * full linux or u-boot support.
+ * The file structure is based on the device tree source for the
+ * Polarfire SoC created by Padmaro Begari. The K210 device trees from
+ * u-boot were originally used to bring up the RTEMS BSP and were
+ * referenced to develop this file.
+ */
+
+/dts-v1/;
+
+/ {
+ /* 32 bit address bus - upper 32 bits are ignored */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Kendtryte K210 generic";
+ compatible = "canaan,kendryte-k210";
+
+ aliases {
+ serial0 = &uarths0;
+ serial1 = &uart1;
+ /* serial2 = &uart2; */
+ /* serial3 = &uart3; */
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ timebase-frequency = <7800000>;
+
+ cpu0: cpu at 0 {
+ compatible = "canaan,k210", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv64imafdc";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu at 1 {
+ compatible = "canaan,k210", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ };
+
+ clocks {
+ in0: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+ };
+
+ sram: memory at 80000000 {
+ device_type = "memory";
+ compatible = "canaan,k210-sram";
+ reg = <0x80000000 0x400000>,
+ <0x80400000 0x200000>,
+ <0x80600000 0x200000>;
+ reg-names = "sram0",
+ "sram1",
+ "aisram";
+
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&plic0>;
+
+ rom0: nvmem at 1000 {
+ reg = <0x1000 0x1000>;
+ read-only;
+ };
+
+ clint0: timer at 2000000 {
+ compatible = "riscv,clint0","sifive,clint0";
+ reg = <0x2000000 0xC000>;
+ interrupts-extended = <&cpu0_intc 3>,<&cpu0_intc 7>,
+ <&cpu1_intc 3>,<&cpu1_intc 7>;
+ };
+
+ plic0: interrupt-controller at c000000 {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "riscv,plic0","sifive,plic-1.0.0";
+ reg = <0xC000000 0x4000000>;
+ riscv,ndev = <65>;
+ interrupt-controller;
+ interrupts-extended =
+ <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
+ };
+
+ uarths0: serial at 38000000 {
+ compatible = "canaan,k210-uarths","sifive,uart0";
+ reg = <0x38000000 0x1000>;
+ interrupts = <33>;
+ clocks = <&sysclk 0>;
+
+ };
+
+ /* apb0 has gpio1 and additional uarts */
+ apb0: bus at 50200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-pm-bus";
+ ranges;
+ clocks = <&sysclk 8>;
+
+ uart1: serial at 50210000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x50210000 0x100>;
+ interrupts = <11>;
+ clocks = <&sysclk 30>,
+ <&sysclk 8>;
+ clock-namees = "baudclk", "abp_pclk";
+ resets = <&sysrst 16>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ };
+ };
+
+ apb1: bus at 50400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-pm-bus";
+ ranges;
+ clocks = <&sysclk 9>;
+
+ sysctl: syscon at 50440000 {
+ compatible = "canaan,k210-sysctl","syscon",
+ "simple-mfd";
+ reg = <0x50440000 0x100>;
+ clocks = <&sysclk 9>;
+ clock-names = "pclk";
+ sysclk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "canaan,k210-rst";
+ clock = <&in0>;
+ };
+ sysrst: reset-coontroller {
+ compatible = "canaan,k210-rst";
+ #reset-cells = <1>;
+ };
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysctl>;
+ offset = <48>;
+ mask = <1>;
+ value = <1>;
+ };
+ };
+ };
+
+ };
+};
diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h
index 911b85f4a3..c33de42aa7 100644
--- a/bsps/riscv/riscv/include/bsp.h
+++ b/bsps/riscv/riscv/include/bsp.h
@@ -60,6 +60,10 @@
#include <rtems/devnull.h>
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+ #include <bsp/k210.h>
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/bsps/riscv/riscv/include/bsp/k210.h b/bsps/riscv/riscv/include/bsp/k210.h
new file mode 100644
index 0000000000..558502cd11
--- /dev/null
+++ b/bsps/riscv/riscv/include/bsp/k210.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup k210_regs
+ *
+ * @brief k210 RISC-V CPU defines.
+ */
+
+/*
+ *
+ * Copyright (c) 2022 Alan Cudmore
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_RISCV_RISCV_K210_H
+#define LIBBSP_RISCV_RISCV_K210_H
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/utility.h>
+
+/**
+ * @defgroup K210 RISC V Register Definitions
+ *
+ * @ingroup RTEMSBSPsriscv
+ *
+ * @brief Register Definitions
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For PLL / Clocks */
+#define K210_SYSCTL_BASE 0x50440000
+
+#define PLL_CLK_R(n) (n & 0x00000F)
+#define PLL_CLK_F(n) ((n & 0x0003F0) >> 4)
+#define PLL_CLK_OD(n) ((n & 0x003C00) >> 10)
+#define CLKSEL0_ACLK_SEL(n) (n & 0x00000001)
+
+typedef struct {
+ uint32_t git_id;
+ uint32_t clk_freq;
+ uint32_t pll0;
+ uint32_t pll1;
+ uint32_t pll2;
+ uint32_t resv5;
+ uint32_t pll_lock;
+ uint32_t rom_error;
+ uint32_t clk_sel0;
+ uint32_t clk_sel1;
+ uint32_t clk_en_cent;
+ uint32_t clk_en_peri;
+ uint32_t soft_reset;
+ uint32_t peri_reset;
+ uint32_t clk_th0;
+ uint32_t clk_th1;
+ uint32_t clk_th2;
+ uint32_t clk_th3;
+ uint32_t clk_th4;
+ uint32_t clk_th5;
+ uint32_t clk_th6;
+ uint32_t misc;
+ uint32_t peri;
+ uint32_t spi_sleep;
+ uint32_t reset_status;
+ uint32_t dma_sel0;
+ uint32_t dma_sel1;
+ uint32_t power_sel;
+ uint32_t resv28;
+ uint32_t resv29;
+ uint32_t resv30;
+ uint32_t resv31;
+} k210_sysctl_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* LIBBSP_RISCV_RISCV_K210_H */
diff --git a/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h
new file mode 100644
index 0000000000..ad13aefdbf
--- /dev/null
+++ b/bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h
@@ -0,0 +1,315 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Declarations for C structure representing binary file system.dtb
+ *
+ * WARNING: Automatically generated -- do not edit!
+ */
+
+/*
+ * Copyright (C) Alan Cudmore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __kendryte_k210_dtb_h
+#define __kendryte_k210_dtb_h
+
+#include <rtems/score/basedefs.h>
+#include <sys/types.h>
+
+const unsigned char system_dtb[] RTEMS_ALIGNED(8) = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x0c, 0xa7, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x0a, 0xb4, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf3,
+ 0x00, 0x00, 0x0a, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x1b,
+ 0x4b, 0x65, 0x6e, 0x64, 0x74, 0x72, 0x79, 0x74, 0x65, 0x20, 0x4b, 0x32,
+ 0x31, 0x30, 0x20, 0x67, 0x65, 0x6e, 0x65, 0x72, 0x69, 0x63, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x21,
+ 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b, 0x65, 0x6e, 0x64, 0x72,
+ 0x79, 0x74, 0x65, 0x2d, 0x6b, 0x32, 0x31, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x01, 0x61, 0x6c, 0x69, 0x61, 0x73, 0x65, 0x73, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x2c,
+ 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40,
+ 0x33, 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x34,
+ 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x62, 0x75, 0x73, 0x40, 0x35, 0x30, 0x32,
+ 0x30, 0x30, 0x30, 0x30, 0x30, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c,
+ 0x40, 0x35, 0x30, 0x32, 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x63, 0x68, 0x6f, 0x73,
+ 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x3c, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x30, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x48,
+ 0x00, 0x77, 0x04, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12,
+ 0x00, 0x00, 0x00, 0x21, 0x63, 0x61, 0x6e, 0x61, 0x61, 0x6e, 0x2c, 0x6b,
+ 0x32, 0x31, 0x30, 0x00, 0x72, 0x69, 0x73, 0x63, 0x76, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x5b,
+ 0x63, 0x70, 0x75, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x6b, 0x72, 0x76, 0x36, 0x34,
+ 0x69, 0x6d, 0x61, 0x66, 0x64, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x40,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x88,
+ 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03,
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+ 0x64, 0x65, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x6e, 0x61, 0x6d,
+ 0x65, 0x73, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x00, 0x23, 0x72, 0x65,
+ 0x73, 0x65, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,
+ 0x67, 0x6d, 0x61, 0x70, 0x00, 0x6f, 0x66, 0x66, 0x73, 0x65, 0x74, 0x00,
+ 0x6d, 0x61, 0x73, 0x6b, 0x00, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x00,
+};
+
+const size_t system_dtb_size = sizeof(system_dtb);
+
+#endif /* __kendryte_k210_dtb_h */
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h
index bbaaa246c1..d294f1ae58 100644
--- a/bsps/riscv/riscv/include/bsp/riscv.h
+++ b/bsps/riscv/riscv/include/bsp/riscv.h
@@ -56,6 +56,10 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
void htif_poweroff(void);
#endif
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void);
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index 30d479ce88..a0b6e683f6 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -201,6 +201,14 @@ static uint32_t get_core_frequency(void)
return fdt32_to_cpu(*val);
}
#endif
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+ uint32_t cpu_clock;
+
+ cpu_clock = k210_get_frequency();
+ return cpu_clock;
+#endif
+
return 0;
}
@@ -215,6 +223,40 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
}
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void)
+{
+ k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
+ uint32_t cpu_clock = 0;
+ uint32_t clk_freq;
+ uint32_t pll0, nr, nf, od;
+ uint32_t node;
+ const char *fdt;
+ const fdt32_t *val;
+ int len;
+
+ fdt = bsp_fdt_get();
+ node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+ val = fdt_getprop(fdt, node, "clock-frequency", &len);
+ if (val != NULL && len == 4) {
+ clk_freq = fdt32_to_cpu(*val);
+
+ if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
+ /* PLL0 selected */
+ pll0 = sysctl->pll0;
+ nr = PLL_CLK_R(pll0) + 1;
+ nf = PLL_CLK_F(pll0) + 1;
+ od = PLL_CLK_OD(pll0) + 1;
+ cpu_clock = (clk_freq / nr * nf / od)/2;
+ } else {
+ /* OSC selected */
+ cpu_clock = clk_freq;
+ }
+ }
+ return cpu_clock;
+}
+#endif
+
void bsp_start(void)
{
riscv_find_harts();
--
2.25.1
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