[PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

[Kinsey Moore]

Philip,
When you get a chance, could you verify that this refactoring meets your
expectations as far as functionality? I'm especially interested in whether
the timer interrupts behave as you expect them to on hardware. I don't mind
getting the Xilinx support code updates committed, but I'd like some
feedback on the BSP itself.

Kinsey

On Thu, Oct 12, 2023 at 12:02 PM Kinsey Moore <kinsey.moore at oarcorp.com>
wrote:

> Changes from v1 (originally submitted by Philip Kirkpatrick):
> Refactoring:
> * import Xilinx code before modification
> * better use the existing Xilinx support code
> Other:
> * An additional patch to add cache support (also from Philip) has been
>   integrated and refactored
>
> This has been tested on Xilinx's QEMU with Xilinx's device tree
> definitions using the following command line options to QEMU:
> -no-reboot -nographic -M arm-generic-fdt -serial null -serial mon:stdio \
> -device loader,file=<RTEMS exe path>,cpu-num=4 \
> -device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \
> -device loader,addr=0xff9a0000,data=0x80000218,data-len=4 \
> -hw-dtb <XLNX DTB dir>/LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \
> -m 4096 -display none
>
> hello.exe and ts-validation-cache.exe operated as expected. Ticker
> produced output, but the timing and content was incorrect on QEMU.
>
>
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