[PATCH 2/3] dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

[Sebastian Huber]

This helps to provide a shared implementation of the kernel I/O support.
---
 bsps/aarch64/xilinx-zynqmp/console/console.c  |  4 ++--
 bsps/arm/xilinx-zynq/console/console-config.c |  5 +++--
 .../console/console-config.c                  |  4 ++--
 .../xilinx-zynqmp/console/console-config.c    |  4 ++--
 spec/build/bsps/objdevserialzynq.yml          |  6 +++++-
 spec/build/bsps/optzynquart0base.yml          | 19 +++++++++++++++++++
 spec/build/bsps/optzynquart1base.yml          | 19 +++++++++++++++++++
 7 files changed, 52 insertions(+), 9 deletions(-)
 create mode 100644 spec/build/bsps/optzynquart0base.yml
 create mode 100644 spec/build/bsps/optzynquart1base.yml

diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c b/bsps/aarch64/xilinx-zynqmp/console/console.c
index 1e5df997e8..ce031a914e 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -188,11 +188,11 @@ RTEMS_SYSINIT_ITEM(
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynq/console/console-config.c b/bsps/arm/xilinx-zynq/console/console-config.c
index d22ceb557d..42e64ee4dd 100644
--- a/bsps/arm/xilinx-zynq/console/console-config.c
+++ b/bsps/arm/xilinx-zynq/console/console-config.c
@@ -35,15 +35,16 @@
 
 #include <bsp/irq.h>
 #include <dev/serial/zynq-uart.h>
+#include <dev/serial/zynq-uart-regs.h>
 
 zynq_uart_context zynq_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xe0000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQ_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xe0001000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQ_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
index eacf6ddcce..13eaa269c5 100644
--- a/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp-rpu/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c b/bsps/arm/xilinx-zynqmp/console/console-config.c
index ea148836a5..787ee05dd6 100644
--- a/bsps/arm/xilinx-zynqmp/console/console-config.c
+++ b/bsps/arm/xilinx-zynqmp/console/console-config.c
@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile struct zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile struct zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };
diff --git a/spec/build/bsps/objdevserialzynq.yml b/spec/build/bsps/objdevserialzynq.yml
index deb3c83a33..ec61f7f545 100644
--- a/spec/build/bsps/objdevserialzynq.yml
+++ b/spec/build/bsps/objdevserialzynq.yml
@@ -12,7 +12,11 @@ install:
   source:
   - bsps/include/dev/serial/zynq-uart-regs.h
   - bsps/include/dev/serial/zynq-uart.h
-links: []
+links:
+- role: build-dependency
+  uid: optzynquart0base
+- role: build-dependency
+  uid: optzynquart1base
 source:
 - bsps/shared/dev/serial/zynq-uart-polled.c
 - bsps/shared/dev/serial/zynq-uart.c
diff --git a/spec/build/bsps/optzynquart0base.yml b/spec/build/bsps/optzynquart0base.yml
new file mode 100644
index 0000000000..1da4e2d1ea
--- /dev/null
+++ b/spec/build/bsps/optzynquart0base.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: bsps/arm/xilinx-zynq
+  value: 0xe0000000
+- enabled-by: true
+  value: 0xff000000
+description: |
+  This option defines the Xilinx Zynq UART 0 base address.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQ_UART_0_BASE_ADDR
+type: build
diff --git a/spec/build/bsps/optzynquart1base.yml b/spec/build/bsps/optzynquart1base.yml
new file mode 100644
index 0000000000..d2b8ae9784
--- /dev/null
+++ b/spec/build/bsps/optzynquart1base.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: bsps/arm/xilinx-zynq
+  value: 0xe0001000
+- enabled-by: true
+  value: 0xff010000
+description: |
+  This option defines the Xilinx Zynq UART 1 base address.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: ZYNQ_UART_1_BASE_ADDR
+type: build
-- 
2.35.3