[PATCH 1/2] hw/intc/arm_gic: Fix set pending of PPIs

[Sebastian Huber]

Sorry, this did go to the wrong mailing list.

On 07.05.24 14:56, Sebastian Huber wrote:
> According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
> Registers, GICD_ISPENDRn":
> 
> "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
> processor. This register holds the Set-pending bits for interrupts 0-31."
> 
> Signed-off-by: Sebastian Huber <sebastian.huber at embedded-brains.de>
> ---
>   hw/intc/arm_gic.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 4da5326ed6..20b3f701e0 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -1296,12 +1296,14 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
>   
>           for (i = 0; i < 8; i++) {
>               if (value & (1 << i)) {
> +                int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
> +
>                   if (s->security_extn && !attrs.secure &&
>                       !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
>                       continue; /* Ignore Non-secure access of Group0 IRQ */
>                   }
>   
> -                GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
> +                GIC_DIST_SET_PENDING(irq + i, cm);
>               }
>           }
>       } else if (offset < 0x300) {

-- 
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