Is there any Guru who knows why interrupts are disabled in ISR?

[Eric Norum]

> I am speeking about the theory. I checked some other CPUs code in RTEMS
> and saw that this is common to all of them.

I don't understand what you're trying to say in the above statement.  
What is `common to all of them'?  The 68k CPU code certainly allows 
high-priority interrupts to preempt low priority interrupt handlers.

--
Eric Norum <eric.norum at usask.ca>
Department of Electrical Engineering
University of Saskatchewan
Saskatoon, Canada.
Phone: (306) 966-5394   FAX:   (306) 966-5407