arm instruction fetch problems

Francesco Poletti fpoletti at
Thu Aug 14 15:54:10 UTC 2003

Hy, I'm looking for someone which know quite well the arm architecture.
I'm simulating an arm6 core with 3 stage of pipeline.

I have this problems: Looking at the trace of the access to the Instruction
cache I can see that my simulator repeate the access at the same address
consecutively. What it means that I make the same IF two times.  If I look at
the branch instruction, for examples, it's splitted in five execution control
stage so I expected to stop the instruction stage for one or two cycle but I
don't expect to redo the same read two times. Is it correct or is a limit of the
arm architecture?
May be that's not the right place where ask this kind of question....
Thanks to all and sorry!


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