PCI caching question related to mvme5500

gregory.menke at gsfc.nasa.gov gregory.menke at gsfc.nasa.gov
Tue Nov 1 18:20:01 UTC 2005

Peter Dufault writes:
 > On Nov 1, 2005, at 11:29 AM, gregory.menke at gsfc.nasa.gov wrote:
 > >
 > > OTOH, maybe the board has an internal buffer that it fills w/ data and
 > > making that part cacheable might expedite copying it off the  
 > > board.  But
 > > I think the OP would be better served by using DMA- my impression  
 > > being
 > > its plain PIO right now, which can cut throughput on the PCI bus by a
 > > factor of 6.
 > >
 > The board has a double-buffered region mapped onto the bus.  When the  
 > data is ready I invalidate the cache every cache line and then memcpy  
 > the data off.  Without reading through a cached region the CPU won't  
 > prefetch and the throughput is terrible.  With it you should be able  
 > to run at PCI memory speed.
 > There are many situations, e.g. small frame sizes as in this case,  
 > where I'd rather have prefetch (and posted writes for output) than DMA.
 > Peter

This is essentially PIO mode, the slowest possible way of getting data
off the PCI bus.  If you're lucky it may burst but you can't confirm
that without a bus analyzer.  This is very likely why you're having
performance issues.  Its cutting your bus throughput by about a factor
of 6.  You should consider using DMA to get your data off the board.


More information about the users mailing list