rtems_semaphore_obtain

[John Pickwick]

Hi,

on that thread, after Jiri's last message, it is unclear to me if there is 
still a problem for LEON2 BSP in the official 4.6.5 release (from RTEMS 
site).

Please can someone clarify this point, thanx

John

----- Original Message ----- 
From: "Joel Sherrill" <joel.sherrill at oarcorp.com>
To: "Thomas Doerfler (nt)" <Thomas.Doerfler at imd-systems.de>
Cc: <rtems-users at rtems.org>
Sent: Thursday, March 29, 2007 10:22 PM
Subject: Re: rtems_semaphore_obtain


> Thomas Doerfler (nt) wrote:
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>> Hi,
>>
>> Some while ago we had a thread on the rtems mailing list which might
>> handle your problem. We found out, that gcc takes the liberty to move
>> some memory accesses that should occure between the irq disable/enable
>> calls to a location before or after the irq disabled section. Try
>> looking for a keyword like "memory barrier" on the mailing list archive 
>> :-)
>>
>>
> This was my first guess also but it fails with the edge of the 4.6 and
> 4.7 branches
> as well as using events for synchronization so it is most likely not the
> barrier problem
> again.
>
> --joel
>> wkr,
>> Thomas.
>>
>>
>> Johan Zandin schrieb:
>>
>>> Sergei Organov  writes:
>>>
>>>
>>>> "Johan Zandin" <johan.zandin at space.se> writes:
>>>>
>>>>
>>>>>       _Context_Switch( &executing->Registers, &heir->Registers );
>>>>>
>>>>>       executing = _Thread_Executing;
>>>>>
>>>>>       _ISR_Disable( level );         -----+
>>>>>                                           |  Region where
>>>>>    }                                      |  an occuring
>>>>>                                           |  interrupt
>>>>>     _Thread_Dispatch_disable_level = 0;   |  causes problems
>>>>>                                           |
>>>>>     _ISR_Enable( level );            -----+
>>>>>
>>>
>>>> But how interrupt can occur when it's disabled in this region?! If
>>>> _ISR_Disable()/_ISR_Enable() don't work on your target, you have hard
>>>> trouble anyway.
>>>>
>>> The HW interrupt occurs but is left pending until ISRs are enabled,
>>> so the ISR does not execute until somewhere within the _ISR_Enable call
>>> (in the first cycle when ISRs are enabled in the CPU again).
>>>
>>> /Johan
>>>
>>> -----------------------------------------------------------
>>> Johan Zandin                      Software Engineer
>>> Saab Space AB                     Phone: +46-31-735 41 47
>>> SE-405 15 Gothenburg, Sweden      Fax:   +46-31-735 40 00
>>> -----------------------------------------------------------
>>>
>>>
>>> _______________________________________________
>>> rtems-users mailing list
>>> rtems-users at rtems.com
>>> http://rtems.rtems.org/mailman/listinfo/rtems-users
>>>
>>
>>
>> - --
>> - --------------------------------------------
>> IMD Ingenieurbuero fuer Microcomputertechnik
>> Thomas Doerfler           Herbststrasse 8
>> D-82178 Puchheim          Germany
>> email:    Thomas.Doerfler at imd-systems.de
>> PGP public key available at:
>>      http://www.imd-systems.de/pgpkey_en.html
>> -----BEGIN PGP SIGNATURE-----
>> Version: GnuPG v1.2.5 (MingW32)
>> Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org
>>
>> iD8DBQFGDBMswHyg4bDtfjQRAshFAJ9CCTaeF89pnc0/43dHX8OzUDnM2QCgjmuz
>> LIoRrwohAlRbJJfF5mPNigk=
>> =ihwI
>> -----END PGP SIGNATURE-----
>> _______________________________________________
>> rtems-users mailing list
>> rtems-users at rtems.com
>> http://rtems.rtems.org/mailman/listinfo/rtems-users
>>
>
> _______________________________________________
> rtems-users mailing list
> rtems-users at rtems.com
> http://rtems.rtems.org/mailman/listinfo/rtems-users
>