Debugging basic BSP tasking functionality

[Matthew J Fletcher]

Hi,

>What do you mean with basic interrupt handlers?
Not using the IRQ exception handler at 0x18, but like so.

--------------------

#define VICVectAddr0    REG32(0xFFFFF100)    /* Vector Address 0 Register */
#define VICIntEnable    REG32(0xFFFFF010)    /* Interrupt Enable Register */
#define VICIntEnClear    REG32(0xFFFFF014)    /* Interrupt Enable Clear
Register */
#define VICIntSelect    REG32(0xFFFFF00C)    /* Interrupt Select Register */

VICIntEnClear = VIC_BIT(VIC_TIMER0);        // Ensure the interrupt is
disabled
...
VICVectAddr0 = (ULONG)tick_handler;        // Address of the ISR
VICIntSelect &= ~VIC_BIT(VIC_TIMER0);        // Timer0 selected as IRQ
VICIntEnable = VIC_BIT(VIC_TIMER0);        // Timer0 interrupt enabled
VICVectCntl0 = VIC_ENABLE | VIC_TIMER0;

---------------------------

>If you want to keep your exception vectors in the flash, then simply use
arm_exc_interrupt >(on 4.10) or _ARMV4_Exception_interrupt (on 4.11) as the
entry point for the interrupt >exception.

Do you mean passing arm_exc_interrupt as the handler into
rtems_interrupt_handler_install()  ? that still gives an unhandled IRQ
exception, probably because there is no handler installed in 0x18.





On 19 April 2013 08:27, Sebastian Huber
<sebastian.huber at embedded-brains.de>wrote:

> On 04/18/2013 07:39 PM, Matthew J Fletcher wrote:
>
>> I've corrected that, no change. I think the issue is that no handler is
>> getting
>> registered. I believe you said previously that ISR_Handler() was the
>> single
>> entry point for all interrupt vectors then it works out what vector its
>> called
>> on and calls the appropriate handler.
>>
>> ARM looks to be the odd one out in that it uses in
>> /cpukit/score/cpu/arm/arm_sec_**interrupt.S
>>
>> I remember now what problem might be, i had to remove the
>> _CPU_ISR_install_vector() call which add arm_exc_interrupt because on my
>> hardware the vector table at 0x0000000 is mapped to on ARM internal flash
>> (which does contain basic interrupt handlers), not RAM.
>>
>
> What do you mean with basic interrupt handlers?  The interrupt
> prologue/epilogue in arm_sec_interrupt.S is there for a purpose.  If you
> want to keep your exception vectors in the flash, then simply use
> arm_exc_interrupt (on 4.10) or _ARMV4_Exception_interrupt (on 4.11) as the
> entry point for the interrupt exception.
>
>
>
>> I've now got a sinking feeling that i cant use rtems on my hardware as
>> is. I
>> suppose this is a question for Sebastian, but when i
>> rtems_interrupt_handler_
>> install() can the handler just be 'arm_exc_interrupt', and the argument
>> the
>> vector number ?
>>
>> I've got my fingers crossed for the answer.
>>
>
> No, this vector is part of the interrupt extension implementation.
>
> http://www.rtems.org/**onlinedocs/doxygen/cpukit/**
> html/group__rtems__interrupt__**extension.html<http://www.rtems.org/onlinedocs/doxygen/cpukit/html/group__rtems__interrupt__extension.html>
>
> You may have a look at (with Doxygen comments):
>
> c/src/lib/libbsp/shared/**include/irq-config.h
> c/src/lib/libbsp/shared/**include/irq-generic.h
> c/src/lib/libbsp/shared/src/**irq-generic.c
> c/src/lib/libbsp/shared/src/**irq-legacy.c
>
> I recommend to use the Git master for ARM.  The current Git master has
> release quality.
>
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-**brains.de<sebastian.huber at embedded-brains.de>
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>



-- 

regards
---
Matthew J Fletcher
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