ARM (Thumb Mode) _CPU_Context_switch_arm
Matthew J Fletcher
amimjf at gmail.com
Mon Feb 25 17:10:36 UTC 2013
The cpsr thats saved out to r2 is 0x800000df, but is restored back to 0x13.
Thanks for pointing out that no cpsr change must happen, i will check how
the rtl22xx_t bsp sets up the cpsr.
On 25 February 2013 16:52, Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:
> On 02/25/2013 05:47 PM, Matthew J Fletcher wrote:
>> r2 is 0x13 before the msr, so I guess new_level must have been 0.
>> On 25 Feb 2013 15:02, "Sebastian Huber" <sebastian.huber at embedded-**
>> brains.de <sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber@**embedded-brains.de<sebastian.huber at embedded-brains.de>>>
>> On 02/25/2013 03:15 PM, Matthew J Fletcher wrote:
>> The _Thread_Heir->Registers are ok into the _Context_Switch()
>> call, sp
>> and lr
>> both sensible.
>> At the 'mrs r2, cpsr' line sp is 0x40001b2c (rubbish) and pc
>> In _restore, after the 'ldmia r1, ...' instruction the sp and lr
>> are loaded
>> with the correct values from _Thread_Heir->Registers.
>> Its the 'msr cpsr, r2' messes up the sp and lr
>> Ok, if you load undefined values into the CPSR, then a lot of things
>> happen. What is the value of r2 before the msr? It should be 0x13.
> Ok, then maybe the mode in the BSP execution context is wrong. During
> _Context_Switch() no mode change must happen. What is the CPSR before the
> Sebastian Huber, embedded brains GmbH
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Matthew J Fletcher
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