Want to add RISC-V-based PolarFire SoC support to RTEMS

[Sebastian Huber]

Hello Padmarao,

On 26/08/2022 13:37, Padmarao.Begari at microchip.com wrote:
> The boot HARTID configurable is Ok but I am thinking about SMP.
> 
> The PolarFire SoC has 4 U54's with hartid 1,2,3,4 but the SMP
> starts with cpu number '0' to MAX cpu number then the PolarFire
> SoC U54's hartid number should become 0,1,2,3 to run the SMP.

the numbers returned by

static inline uint32_t _CPU_SMP_Get_current_processor( void )
{
   unsigned long mhartid;

   __asm__ volatile (
     ".option push\n"
     ".option arch, +zicsr\n"
     "csrr %0, mhartid\n"
     ".option pop" :
     "=&r" ( mhartid )
   );

   return (uint32_t) mhartid;
}

must be in the range 0, ..., CPU count - 1. For your chip you need 
something like

static inline uint32_t _CPU_SMP_Get_current_processor( void )
{
   unsigned long mhartid;

   __asm__ volatile (
     ".option push\n"
     ".option arch, +zicsr\n"
     "csrr %0, mhartid\n"
     ".option pop" :
     "=&r" ( mhartid )
   );

   return (uint32_t) mhartid + RISCV_MHARTID_OFFSET;
}

The RISCV_MHARTID_OFFSET could be a new CPU option which has 
BSP-dependent default values. It would be the first CPU option in RTEMS 
with BSP-dependent default values.

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