[PATCH] bsps/arm: Improve GICv3 support

[Kinsey Moore]

This adds warnings for arm_interrupt_enable_interrupts and
arm_interrupt_restore_interrupts. I suspect a missing header. They also
generate a link error on the a53_lp64_qemu bsp. I also dislike the
while(true), but I don't think we officially have anything against it and
there are existing examples in the codebase.

Kinsey

On Tue, Apr 16, 2024 at 3:24 AM Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:

> In addtion to 1023, the GICC_IAR register may return 1022 as a special
> value.
> Simply check for a valid interrupt vector for the dispatching.
>
> Check the GICC_IAR again after the dispatch to quickly process a next
> interrupt
> without having to go through the interrupt prologue and epiloge.
> ---
>  bsps/shared/dev/irq/arm-gicv3.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/bsps/shared/dev/irq/arm-gicv3.c
> b/bsps/shared/dev/irq/arm-gicv3.c
> index 88ac3c8293..dcfada6cd0 100644
> --- a/bsps/shared/dev/irq/arm-gicv3.c
> +++ b/bsps/shared/dev/irq/arm-gicv3.c
> @@ -42,12 +42,18 @@
>
>  void bsp_interrupt_dispatch(void)
>  {
> -  uint32_t icciar = READ_SR(ICC_IAR1);
> -  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
> -  rtems_vector_number spurious = 1023;
> +  while (true) {
> +    uint32_t icciar = READ_SR(ICC_IAR1);
> +    rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
> +    uint32_t status;
>
> -  if (vector != spurious) {
> -    arm_interrupt_handler_dispatch(vector);
> +    if (!bsp_interrupt_is_valid_vector(vector)) {
> +      break;
> +    }
> +
> +    status = arm_interrupt_enable_interrupts();
> +    bsp_interrupt_handler_dispatch_unchecked(vector);
> +    arm_interrupt_restore_interrupts(status);
>
>      WRITE_SR(ICC_EOIR1, icciar);
>    }
> --
> 2.35.3
>
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