Acessing PL devices of Xilinx Zedboard

[Jonathan Brandmeyer]

On Wed, Nov 18, 2020 at 8:37 AM <Jan.Sommer at dlr.de> wrote:

> Hello,
>
> We try to use the xilinx_zynq_zedboard BSP with some devices synthesized
> to the PL, e.g. a Xilinx NS16550 Uart.
> If I try to access any of the AXI registers, I get a fatal error with a
> vector number 0x04 (undefined instruction).
> Accessing the same register address from within a Xilinx standalone
> hello-world program works as expected.
> Could it be that during the RTEMS startup some of the system
> initialization is reset so that accessing the PL devices fails?
>


The default memory map does not provide access to any of the PL address
range.  You'll have to override the weak symbol zynq_setup_mmu_and_cache to
provide your own memory map.  The MMU code only supports 1 MB superpages at
this time.

Caveat: My information could be a little out of date.  We're still running
on a pre-release version of RTEMS 5.0.  But hopefully this points you in
the right direction.  In particular, I know that some work has been done to
support 4kB pages, but I don't know if the entry point
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache currently
uses that support or not.

-- 
Jonathan Brandmeyer
PlanetiQ
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