Handling RISC-V32 interrupts and traps, mcause mapping for rtems_interrupt_catch()
Schweikhardt, Jens (TSPCE3-TL4)
Jens.Schweikhardt at tesat.de
Tue May 25 12:26:13 UTC 2021
Hello *,
I'm trying to install interrupt and trap handlers for interrupts and
traps not used by RTEMS 5 on a RISC-V32 rocket chip system.
In "Volume II: RISC-V Privileged Architectures" I found
"Table 3.6: Machine cause register (mcause) values." listing
the interrupts and traps:
Interrupt Exception Code Description
1 0 User software interrupt
1 1 Supervisor software interrupt
1 2 Hypervisor software interrupt
1 3 Machine software interrupt
1 4 User timer interrupt
1 5 Supervisor timer interrupt
1 6 Hypervisor timer interrupt
1 7 Machine timer interrupt
1 8 User external interrupt
1 9 Supervisor external interrupt
1 10 Hypervisor external interrupt
1 11 Machine external interrupt
1 >=12 Reserved
0 0 Instruction address misaligned
0 1 Instruction access fault
0 2 Illegal instruction
0 3 Breakpoint
0 4 Load address misaligned
0 5 Load access fault
0 6 Store/AMO address misaligned
0 7 Store/AMO access fault
0 8 Environment call from U-mode
0 9 Environment call from S-mode
0 10 Environment call from H-mode
0 11 Environment call from M-mode
0 >=12 Reserved
The RTEMS RISC-V docs specify that unhandled exceptions invoke
the fatal error handler with RTEMS_FATAL_SOURCE_EXCEPTION.
I want to change this so a custom handler is called. I believe
I should use rtems_interrupt_catch(handler, <number>, &old)
but I am unsure what number to use for interrupt versus trap from
the table above. E.g. how would I install a handler for, say,
interrupt 11 (Machine external interrup) and how for
trap 11 (Environment call from M-mode)?
Which of these are used by RTEMS and should not be touched?
Thanks for any hints.
Regards,
Jens
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